mirror of
https://github.com/RIOT-OS/RIOT.git
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05f114d0af
- most were trivial
- missing group close or open
- extra space
- no doxygen comment
- name commad might open an implicit group
this hould also be implicit cosed but does not happen somtimes
- crazy: internal declared groups have to be closed internal
257 lines
7.0 KiB
C
257 lines
7.0 KiB
C
/*
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* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_lpc23xx
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "cpu.h"
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/**
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* @brief LPC2387 MCU defines
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* @{
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*/
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#define __IO volatile
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/** @} */
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/**
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* @name Power mode configuration
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* @{
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*/
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#define PM_NUM_MODES (4)
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/** @} */
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/**
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* @brief Fast GPIO register definition struct
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*/
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typedef struct {
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/** @brief Direction: Output if corresponding bit is set, otherwise input */
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__IO uint32_t DIR;
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/** @brief 12 bytes of reserved memory we don't need to access */
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uint32_t _reserved[3];
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/** @brief Set bits to ignore corresponding bits when accessing `PIN`, `SET`
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* or `CLR` register of this port
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*/
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__IO uint32_t MASK;
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/** @brief The current state of each pin of this port is accessible here
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* (regardless of direction): If bit is set input is high
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*/
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__IO uint32_t PIN;
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/** @brief Output pins are set to high by setting the corresponding bit */
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__IO uint32_t SET;
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/** @brief Output pins are set to low by setting the corresponding bit */
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__IO uint32_t CLR;
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} FIO_PORT_t;
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/**
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* @brief Pointer to the Fast GPIO register
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*/
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#define FIO_PORTS ((FIO_PORT_t*)FIO_BASE_ADDR)
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/**
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* @brief Pointer to the PINSEL register
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*/
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#define PINSEL ((__IO uint32_t *)(PINSEL_BASE_ADDR))
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/**
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* @brief Pointer to the PINMODE register
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*/
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#define PINMODE ((__IO uint32_t *)(PINSEL_BASE_ADDR + 0x40))
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/**
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* @brief Set up alternate function (PMUX setting) for a PORT pin
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*
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* @param[in] pin Pin to set the multiplexing for
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* @param[in] mux Mux value
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*/
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int gpio_init_mux(unsigned pin, unsigned mux);
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/**
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* @brief Macro for accessing GPIO pins
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*/
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#define GPIO_PIN(port, pin) (port<<5 | pin)
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#ifndef DOXYGEN
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_FALLING = 1, /**< emit interrupt on falling flank */
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GPIO_RISING = 2, /**< emit interrupt on rising flank */
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GPIO_BOTH = 3 /**< emit interrupt on both flanks */
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} gpio_flank_t;
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#endif /* ifndef DOXYGEN */
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/**
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* @brief UART device configuration
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*/
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typedef struct {
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lpc23xx_uart_t *dev; /**< pointer to the UART device */
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uint8_t irq_prio_rx; /**< priority of the RX IRQ */
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uint8_t pinsel_rx; /**< PINSEL# of the RX pin */
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uint8_t pinsel_tx; /**< PINSEL# of the TX pin */
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uint32_t pinsel_msk_rx; /**< RX PINSEL Mask */
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uint32_t pinsel_msk_tx; /**< TX PINSEL Mask */
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} uart_conf_t;
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/**
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* @brief SPI device configuration
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*/
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typedef struct {
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lpc23xx_spi_t *dev; /**< pointer to the SPI device */
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uint8_t pinsel_mosi; /**< PINSEL# of the MOSI pin */
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uint8_t pinsel_miso; /**< PINSEL# of the MISO pin */
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uint8_t pinsel_clk; /**< PINSEL# of the CLK pin */
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uint32_t pinsel_msk_mosi; /**< MOSI PINSEL Mask */
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uint32_t pinsel_msk_miso; /**< MISO PINSEL Mask */
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uint32_t pinsel_msk_clk; /**< CLK PINSEL Mask */
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} spi_conf_t;
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/**
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* @brief Number of available timer channels
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*/
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#define TIMER_CHANNEL_NUMOF (4U)
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/**
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* @brief Prevent shared timer functions from being used
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*/
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#define PERIPH_TIMER_PROVIDES_SET
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/**
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* @brief Declare needed generic SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_INIT_CS
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/** @} */
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#ifndef DOXYGEN
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/**
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* @brief Override SPI clock speed values
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* @{
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = 100, /**< drive the SPI bus with 100KHz */
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SPI_CLK_400KHZ = 400, /**< drive the SPI bus with 400KHz */
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SPI_CLK_1MHZ = 1000, /**< drive the SPI bus with 1MHz */
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SPI_CLK_5MHZ = 5000, /**< drive the SPI bus with 5MHz */
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SPI_CLK_10MHZ = 10000 /**< drive the SPI bus with 10MHz */
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} spi_clk_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief DAC configuration, valid for all boards using this CPU
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*
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* lpc23xx has a fixed mapping of DAC pins and a fixed number of DAC channels,
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* so this DAC configuration is valid for all boards using this CPU. No need for
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* any board specific configuration.
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*
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* The DAC of the lpc23xx is mapped to the following fixed pin:
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* - line 0 (ch0): P0.26
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*/
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#define DAC_NUMOF (1U)
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#ifndef DOXYGEN
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/**
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* @brief Possible ADC resolution settings
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* @{
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*/
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#define HAVE_ADC_RES_T
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typedef enum {
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ADC_RES_16BIT = 0xff, /**< not applicable */
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ADC_RES_14BIT = 0xfe, /**< not applicable */
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ADC_RES_12BIT = 0xfd, /**< not applicable */
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ADC_RES_10BIT = 0b000, /**< ADC resolution: 10 bit */
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ADC_RES_9BIT = 0b001, /**< ADC resolution: 9 bit */
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ADC_RES_8BIT = 0b010, /**< ADC resolution: 8 bit */
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ADC_RES_7BIT = 0b011, /**< ADC resolution: 7 bit */
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ADC_RES_6BIT = 0b100, /**< ADC resolution: 6 bit */
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ADC_RES_5BIT = 0b101, /**< ADC resolution: 5 bit */
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ADC_RES_4BIT = 0b110, /**< ADC resolution: 4 bit */
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ADC_RES_3BIT = 0b111, /**< ADC resolution: 3 bit */
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} adc_res_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief ADC device configuration
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*/
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typedef struct {
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uint8_t chan; /**< which ADC to use (0…7) */
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uint8_t pinsel; /**< PINSEL# of the ADC pin */
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uint32_t pinsel_msk; /**< PINSEL Mask for ADC pin */
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} adc_conf_t;
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#ifndef DOXYGEN
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/**
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* @brief Override I2C clock speed values
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* @{
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*/
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#define HAVE_I2C_SPEED_T
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typedef enum {
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I2C_SPEED_LOW = 10000, /**< low speed mode: ~10 kbit/s */
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I2C_SPEED_NORMAL = 100000, /**< normal mode: ~100 kbit/s */
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I2C_SPEED_FAST = 400000, /**< fast mode: ~400 kbit/s */
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} i2c_speed_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief I2C device configuration
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*/
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typedef struct {
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lpc23xx_i2c_t *dev; /**< pointer to the I2C device */
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i2c_speed_t speed; /**< I2C bus speed */
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uint8_t irq_prio; /**< priority of the I2C IRQ */
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uint8_t pinsel_sda; /**< PINSEL# of the SDA pin */
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uint8_t pinsel_scl; /**< PINSEL# of the SCL pin */
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uint32_t pinsel_msk_sda;/**< SDA PINSEL Mask */
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uint32_t pinsel_msk_scl;/**< SCL PINSEL Mask */
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} i2c_conf_t;
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/**
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* @name Use shared I2C functions
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* @{
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*/
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#define PERIPH_I2C_NEED_READ_REG
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#define PERIPH_I2C_NEED_WRITE_REG
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/** @} */
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/**
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* Enable yday and wday calculation in rtc_normalize().
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* Those fields are used by the RTC.
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* @{
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*/
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#if defined(MODULE_PERIPH_RTC) && !defined(RTC_NORMALIZE_COMPAT)
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#define RTC_NORMALIZE_COMPAT (1)
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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