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78 lines
2.0 KiB
C
78 lines
2.0 KiB
C
/*
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* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_lm4f120
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* @{
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*
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* @file cpu.c
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* @brief Implementation of the CPU initialization
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*
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* @author Rakendra Thapa <rakendrathapa@gmail.com>
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* @}
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*/
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#include "cpu.h"
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#include "kernel_init.h"
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#include "irq.h"
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#include "sched.h"
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#include "thread.h"
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#include "irq.h"
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#include "periph/init.h"
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#include "periph_conf.h"
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#include "stdio_base.h"
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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/* initializes the Cortex-M core */
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cortexm_init();
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/* initialize the clock system */
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cpu_clock_init(CLOCK_SOURCE);
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/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
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early_init();
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/* trigger static peripheral initialization */
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periph_init();
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}
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void setup_fpu(void)
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{
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ROM_FPUEnable();
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ROM_FPULazyStackingEnable();
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}
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void cpu_clock_init(int clk)
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{
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setup_fpu();
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switch(clk){
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case CLK80:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
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break;
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case CLK50:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
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break;
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case CLK40:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
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break;
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case CLK16:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
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break;
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case CLK1:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_1MHZ | SYSCTL_OSC_MAIN);
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break;
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default:
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
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break;
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}
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}
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