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RIOT/cpu/esp32/periph/gpio_ll_irq.c
Marian Buschsieweke 36e8526046
drivers/periph_gpio_ll: change API to access GPIO ports
The API was based on the assumption that GPIO ports are mapped in memory
sanely, so that a `GPIO_PORT(num)` macro would work allow for constant
folding when `num` is known and still be efficient when it is not.

Some MCUs, however, will need a look up tables to efficiently translate
GPIO port numbers to the port's base address. This will prevent the use
of such a `GPIO_PORT(num)` macro in constant initializers.

As a result, we rather provide `GPIO_PORT_0`, `GPIO_PORT_1`, etc. macros
for each GPIO port present (regardless of MCU naming scheme), as well as
`GPIO_PORT_A`, `GPIO_PORT_B`, etc. macros if (and only if) the MCU port
naming scheme uses letters rather than numbers.

These can be defined as macros to the peripheral base address even when
those are randomly mapped into the address space. In addition, a C
function `gpio_port()` replaces the role of the `GPIO_PORT()` and
`gpio_port_num()` the `GPIO_PORT_NUM()` macro. Those functions will
still be implemented as efficient as possible and will allow constant
folding where it was formerly possible. Hence, there is no downside for
MCUs with sane peripheral memory mapping, but it is highly beneficial
for the crazy ones.

There are also two benefits for the non-crazy MCUs:
1. We can now test for valid port numbers with `#ifdef GPIO_PORT_<NUM>`
    - This directly benefits the test in `tests/periph/gpio_ll`, which
      can now provide a valid GPIO port for each and every board
    - Writing to invalid memory mapped I/O addresses was treated as
      triggering undefined behavior by the compiler and used as a
      optimization opportunity
2. We can now detect at compile time if the naming scheme of the MCU
   uses letters or numbers, and produce more user friendly output.
    - This is directly applied in the test app
2024-08-02 09:55:24 +02:00

158 lines
3.9 KiB
C

/*
* Copyright (C) 2021 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_esp32
* @ingroup drivers_periph_gpio_ll_irq
* @{
*
* @file
* @brief IRQ implementation of the GPIO Low-Level API for ESP32
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @}
*/
#define ENABLE_DEBUG 0
#include "debug.h"
#include <assert.h>
#include <stdbool.h>
#include "log.h"
#include "periph/gpio_ll_irq.h"
#include "esp/common_macros.h"
#include "esp_intr_alloc.h"
#include "hal/gpio_hal.h"
#include "hal/gpio_types.h"
#include "rom/ets_sys.h"
#if __xtensa__
#include "xtensa/xtensa_api.h"
#endif
#include "esp_idf_api/gpio.h"
#include "irq_arch.h"
#if MODULE_PERIPH_GPIO_IRQ
/* variables that have to be used together with periph/gpio_irq */
extern bool gpio_int_enabled_table[];
extern bool gpio_isr_service_installed;
#else
bool gpio_int_enabled_table[GPIO_PIN_NUMOF] = { };
bool gpio_isr_service_installed = false;
#endif
extern void IRAM gpio_int_handler(void* arg);
int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig,
gpio_ll_cb_t cb, void *arg)
{
assert(is_gpio_port_num_valid(port));
assert(arg);
assert(pin < GPIO_PORT_PIN_NUMOF(port));
unsigned state = irq_disable();
gpio_t gpio = GPIO_PIN(gpio_port_num(port), pin);
DEBUG("%s gpio=%u port=%u pin=%u trig=%d cb=%p arg=%p\n",
__func__, gpio, (unsigned)gpio_port_num(port), pin, trig, cb, arg);
/* install GPIO ISR of ESP-IDF if not yet done */
if (!gpio_isr_service_installed &&
esp_idf_gpio_install_isr_service(ESP_INTR_FLAG_LEVEL1) != ESP_OK) {
return -1;
}
gpio_isr_service_installed = true;
/* set the interrupt type for the pin */
gpio_int_type_t type;
switch (trig) {
case GPIO_TRIGGER_EDGE_FALLING:
type = GPIO_INTR_NEGEDGE;
break;
case GPIO_TRIGGER_EDGE_RISING:
type = GPIO_INTR_POSEDGE;
break;
case GPIO_TRIGGER_EDGE_BOTH:
type = GPIO_INTR_ANYEDGE;
break;
case GPIO_TRIGGER_LEVEL_HIGH:
type = GPIO_INTR_HIGH_LEVEL;
break;
case GPIO_TRIGGER_LEVEL_LOW:
type = GPIO_INTR_LOW_LEVEL;
break;
default:
type = GPIO_INTR_DISABLE;
}
if (esp_idf_gpio_set_intr_type(gpio, type) != ESP_OK) {
return -1;
}
/* add interrupt handler for the pin */
if (esp_idf_gpio_isr_handler_add(gpio, cb, arg) != ESP_OK) {
return -1;
}
/* unmask and clear pending interrupts for the pin */
gpio_ll_irq_unmask_and_clear(port, pin);
irq_restore(state);
return 0;
}
void gpio_ll_irq_mask(gpio_port_t port, uint8_t pin)
{
gpio_t gpio = GPIO_PIN(gpio_port_num(port), pin);
DEBUG("%s gpio=%u port=%u pin=%u\n",
__func__, gpio, (unsigned)gpio_port_num(port), pin);
if (esp_idf_gpio_intr_disable(gpio) == ESP_OK) {
gpio_int_enabled_table[gpio] = false;
}
}
void gpio_ll_irq_unmask(gpio_port_t port, uint8_t pin)
{
gpio_t gpio = GPIO_PIN(gpio_port_num(port), pin);
DEBUG("%s gpio=%u port=%u pin=%u\n",
__func__, gpio, port, pin);
if (esp_idf_gpio_intr_enable(gpio) == ESP_OK) {
gpio_int_enabled_table[gpio] = true;
}
}
void gpio_ll_irq_unmask_and_clear(gpio_port_t port, uint8_t pin)
{
gpio_t gpio = GPIO_PIN(gpio_port_num(port), pin);
DEBUG("%s gpio=%u port=%u pin=%u\n",
__func__, gpio, (unsigned)gpio_port_num(port), pin);
volatile uint32_t *status_w1tc = (uint32_t *)GPIO_STATUS_W1TC_REG;
#if GPIO_PORT_NUMOF > 1
if (gpio_port_num(port) != 0) {
status_w1tc = (uint32_t *)GPIO_STATUS1_W1TC_REG;
}
#endif
*status_w1tc = BIT(pin);
if (esp_idf_gpio_intr_enable(gpio) == ESP_OK) {
gpio_int_enabled_table[gpio] = true;
}
}