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55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/*
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* Copyright (C) 2015 INRIA
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* Copyright (C) 2015 Eistec AB
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* Copyright (C) 2016 OTA keys
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_cortexm_common
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* @{
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*
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* @file
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* @brief Crash handling functions implementation for ARM Cortex-based MCUs
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*
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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* @author Toon Stegen <toon.stegen@altran.com>
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*/
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#include <stdio.h>
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#include "cpu.h"
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#ifdef DEVELHELP
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static void print_ipsr(void)
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{
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uint32_t ipsr = __get_IPSR() & IPSR_ISR_Msk;
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if (ipsr) {
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/* if you get here, you might have forgotten to implement the isr
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* for the printed interrupt number */
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printf("Inside isr %d\n", ((int)ipsr) - 16);
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}
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}
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#endif
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void panic_arch(void)
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{
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#ifdef DEVELHELP
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print_ipsr();
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/* CM0+ has a C_DEBUGEN bit but it is NOT accessible by CPU (only by debugger) */
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#ifdef CoreDebug_DHCSR_C_DEBUGEN_Msk
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if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) {
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/* if Debug session is running, tell the debugger to break here.
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Skip it otherwise as this instruction will cause either a fault
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escalation to hardfault or a CPU lockup */
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__asm__("bkpt #0");
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}
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#endif /* CoreDebug_DHCSR_C_DEBUGEN_Msk */
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#endif
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}
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