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becca71caf
> Fixes a typo on XOSC selection bitfield that would make the CPU crash when changing it. > Sets the other fields to their default values. Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
292 lines
15 KiB
C
292 lines
15 KiB
C
/*
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* Copyright (C) 2016 Leon George
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* Copyright (C) 2020 Locha Inc
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc26xx_cc13xx
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* @{
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*
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* @file
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* @brief Interrupt vector definitions
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*
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* @author Leon M. George <leon@georgemail.eu>
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* @author Anton Gerasimov <tossel@gmail.com>
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* @author Jean Pierre Dudey <jeandudey@hotmail.com>
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "board.h"
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#include "vectors_cortexm.h"
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* CC26xx_CC13xx specific interrupt vectors */
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WEAK_DEFAULT void isr_edge(void);
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WEAK_DEFAULT void isr_i2c(void);
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WEAK_DEFAULT void isr_rfc_cpe1(void);
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WEAK_DEFAULT void isr_pka(void);
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WEAK_DEFAULT void isr_aon_rtc(void);
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WEAK_DEFAULT void isr_uart0(void);
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WEAK_DEFAULT void isr_aux0_aon(void);
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WEAK_DEFAULT void isr_ssi0(void);
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WEAK_DEFAULT void isr_ssi1(void);
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WEAK_DEFAULT void isr_rfc_cpe0(void);
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WEAK_DEFAULT void isr_rfc_hw(void);
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WEAK_DEFAULT void isr_rfc_cmd_ack(void);
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WEAK_DEFAULT void isr_i2s(void);
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WEAK_DEFAULT void isr_aux1_aon(void);
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WEAK_DEFAULT void isr_watchdog(void);
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WEAK_DEFAULT void isr_timer0_chan0(void);
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WEAK_DEFAULT void isr_timer0_chan1(void);
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WEAK_DEFAULT void isr_timer1_chan0(void);
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WEAK_DEFAULT void isr_timer1_chan1(void);
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WEAK_DEFAULT void isr_timer2_chan0(void);
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WEAK_DEFAULT void isr_timer2_chan1(void);
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WEAK_DEFAULT void isr_timer3_chan0(void);
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WEAK_DEFAULT void isr_timer3_chan1(void);
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WEAK_DEFAULT void isr_crypto_res(void);
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WEAK_DEFAULT void isr_dma(void);
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WEAK_DEFAULT void isr_dmaerr(void);
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WEAK_DEFAULT void isr_flash(void);
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WEAK_DEFAULT void isr_se0(void);
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WEAK_DEFAULT void isr_aux_ce(void);
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WEAK_DEFAULT void isr_aon_prog(void);
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WEAK_DEFAULT void isr_dyn_prog(void);
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WEAK_DEFAULT void isr_comp(void);
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WEAK_DEFAULT void isr_adc(void);
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WEAK_DEFAULT void isr_trng(void);
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#ifdef CPU_VARIANT_X2
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WEAK_DEFAULT void isr_osc(void);
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WEAK_DEFAULT void isr_aux_timer2(void);
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WEAK_DEFAULT void isr_uart1(void);
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WEAK_DEFAULT void isr_batmon(void);
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#endif // CPU_VARIANT_X2
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[] = {
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isr_edge, /* 16 AON edge detect */
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isr_i2c, /* 17 I2C */
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isr_rfc_cpe1, /* 18 RF Command and Packet Engine 1 */
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isr_pka, /* 19 PKA interrupt */
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isr_aon_rtc, /* 20 AON RTC */
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isr_uart0, /* 21 UART0 Rx and Tx */
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isr_aux0_aon, /* 22 AUX event 0, through AON domain */
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isr_ssi0, /* 23 SSI0 Rx and Tx */
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isr_ssi1, /* 24 SSI1 Rx and Tx */
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isr_rfc_cpe0, /* 25 RF Command and Packet Engine 0 */
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isr_rfc_hw, /* 26 RF Core Hardware */
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isr_rfc_cmd_ack, /* 27 RF Core Command Acknowledge */
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isr_i2s, /* 28 I2S */
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isr_aux1_aon, /* 29 AUX event 1, through AON domain */
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isr_watchdog, /* 30 Watchdog timer */
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isr_timer0_chan0, /* 31 Timer 0 subtimer A */
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isr_timer0_chan1, /* 32 Timer 0 subtimer B */
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isr_timer1_chan0, /* 33 Timer 1 subtimer A */
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isr_timer1_chan1, /* 34 Timer 1 subtimer B */
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isr_timer2_chan0, /* 35 Timer 2 subtimer A */
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isr_timer2_chan1, /* 36 Timer 2 subtimer B */
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isr_timer3_chan0, /* 37 Timer 3 subtimer A */
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isr_timer3_chan1, /* 38 Timer 3 subtimer B */
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isr_crypto_res, /* 39 Crypto Core Result available */
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isr_dma, /* 40 uDMA Software */
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isr_dmaerr, /* 41 uDMA Error */
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isr_flash, /* 42 Flash controller */
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isr_se0, /* 43 Software Event 0 */
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isr_aux_ce, /* 44 AUX combined event, directly to MCU domain */
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isr_aon_prog, /* 45 AON programmable 0 */
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isr_dyn_prog, /* 46 Dynamic Programmable interrupt (default source: PRCM) */
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isr_comp, /* 47 AUX Comparator A */
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isr_adc, /* 48 AUX ADC IRQ */
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isr_trng, /* 49 TRNG event */
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#ifdef CPU_VARIANT_X2
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isr_osc, /* 50 Combined event from oscillator control */
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isr_aux_timer2, /* 51 AUX Timer 2 event 0 */
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isr_uart1, /* 52 UART 1 RX and TX */
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isr_batmon, /* 53 BATMON interrupt */
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#endif // CPU_VARIANT_X2
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};
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#if IS_USED(CONFIG_CC26XX_CC13XX_UPDATE_CCFG)
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/**
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* @brief Set the bits of a CCFG bit field.
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*
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* Allows safe concatenation of values and protects with the mask
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* from setting unwanted bits.
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*
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* Example:
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ {.c}
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* uint32_t value = CCFG_SET_BITS(0xCA, 24, 0xFF000000)
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& CCFG_SET_BITS(0xFE, 16, 0x00FF0000);
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* @param value The bit value to set.
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* @param shift_amount The (to left) shift amount.
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* @param mask The bit mask.
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*/
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#define CCFG_SET_BITS(value, shift_amount, mask) \
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(((uint32_t)(value)) << (shift_amount) | ~(mask))
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extern cortexm_base_t cortex_vector_base;
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__attribute__((section(".ccfg"), used))
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ccfg_regs_t cc26xx_cc13xx_ccfg = {
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/* external LF clock configuration */
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.EXT_LF_CLK = CCFG_SET_BITS(SET_EXT_LF_CLK_DIO,
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CCFG_EXT_LF_CLK_DIO_s,
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CCFG_EXT_LF_CLK_DIO_m)
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& CCFG_SET_BITS(SET_EXT_LF_CLK_RTC_INCREMENT,
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CCFG_EXT_LF_CLK_RTC_INCREMENT_s,
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CCFG_EXT_LF_CLK_RTC_INCREMENT_m),
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/* misc */
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.MODE_CONF_1 =
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#ifdef CPU_VARIANT_X2
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/* only x2 CPUs allow TCXO settings */
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CCFG_SET_BITS(SET_MODE_CONF_1_TCXO_TYPE,
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CCFG_MODE_CONF_1_TCXO_TYPE_s,
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CCFG_MODE_CONF_1_TCXO_TYPE_m)
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& CCFG_SET_BITS(SET_MODE_CONF_1_TCXO_MAX_START,
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CCFG_MODE_CONF_1_TCXO_MAX_START_s,
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CCFG_MODE_CONF_1_TCXO_MAX_START_m)
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& CCFG_SET_BITS(SET_MODE_CONF_1_ALT_DCDC_VMIN,
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CCFG_MODE_CONF_1_ALT_DCDC_VMIN_s,
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CCFG_MODE_CONF_1_ALT_DCDC_VMIN_m)
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#else
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CCFG_SET_BITS(SET_MODE_CONF_1_ALT_DCDC_VMIN,
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CCFG_MODE_CONF_1_ALT_DCDC_VMIN_s,
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CCFG_MODE_CONF_1_ALT_DCDC_VMIN_m)
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#endif /* CPU_VARIANT_X2 */
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& CCFG_SET_BITS(SET_MODE_CONF_1_ALT_DCDC_DITHER_EN,
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CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_s,
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CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_m)
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& CCFG_SET_BITS(SET_MODE_CONF_1_ALT_DCDC_IPEAK,
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CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_s,
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CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_m)
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& CCFG_SET_BITS(SET_MODE_CONF_1_DELTA_IBIAS_INIT,
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CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_s,
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CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_m)
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& CCFG_SET_BITS(SET_MODE_CONF_1_DELTA_IBIAS_OFFSET,
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CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_s,
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CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_m)
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& CCFG_SET_BITS(SET_MODE_CONF_1_XOSC_MAX_START,
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CCFG_MODE_CONF_1_XOSC_MAX_START_s,
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CCFG_MODE_CONF_1_XOSC_MAX_START_m),
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/* misc */
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.SIZE_AND_DIS_FLAGS = CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG,
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CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_s,
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CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_m)
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& CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS,
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CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_s,
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CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_m)
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& CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_DIS_TCXO,
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CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_s,
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CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_m)
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& CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM,
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CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_s,
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CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_m)
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& CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING,
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CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_s,
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CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_m)
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& CCFG_SET_BITS(SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR,
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CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_s,
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CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_m),
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/* misc */
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.MODE_CONF = CCFG_SET_BITS(SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA,
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CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_s,
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CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_m)
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& CCFG_SET_BITS(SET_MODE_CONF_DCDC_RECHARGE,
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CCFG_MODE_CONF_DCDC_RECHARGE_s,
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CCFG_MODE_CONF_DCDC_RECHARGE_m)
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& CCFG_SET_BITS(SET_MODE_CONF_DCDC_ACTIVE,
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CCFG_MODE_CONF_DCDC_ACTIVE_s,
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CCFG_MODE_CONF_DCDC_ACTIVE_m)
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& CCFG_SET_BITS(SET_MODE_CONF_VDDR_EXT_LOAD,
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CCFG_MODE_CONF_VDDR_EXT_LOAD_s,
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CCFG_MODE_CONF_VDDR_EXT_LOAD_m)
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& CCFG_SET_BITS(SET_MODE_CONF_VDDS_BOD_LEVEL,
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CCFG_MODE_CONF_VDDS_BOD_LEVEL_s,
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CCFG_MODE_CONF_VDDS_BOD_LEVEL_m)
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& CCFG_SET_BITS(SET_MODE_CONF_SCLK_LF_OPTION,
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CCFG_MODE_CONF_SCLK_LF_OPTION_s,
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CCFG_MODE_CONF_SCLK_LF_OPTION_m)
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& CCFG_SET_BITS(SET_MODE_CONF_VDDR_TRIM_SLEEP_TC,
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CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_s,
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CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_m)
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& CCFG_SET_BITS(SET_MODE_CONF_RTC_COMP,
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CCFG_MODE_CONF_RTC_COMP_s,
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CCFG_MODE_CONF_RTC_COMP_m)
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& CCFG_SET_BITS(SET_MODE_CONF_XOSC_FREQ,
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CCFG_MODE_CONF_XOSC_FREQ_s,
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CCFG_MODE_CONF_XOSC_FREQ_m)
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& CCFG_SET_BITS(SET_MODE_CONF_XOSC_CAP_MOD,
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CCFG_MODE_CONF_XOSC_CAP_MOD_s,
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CCFG_MODE_CONF_XOSC_CAP_MOD_m)
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& CCFG_SET_BITS(SET_MODE_CONF_HF_COMP,
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CCFG_MODE_CONF_HF_COMP_s,
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CCFG_MODE_CONF_HF_COMP_m)
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& CCFG_SET_BITS(SET_MODE_CONF_XOSC_CAPARRAY_DELTA,
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CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_s,
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CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_m)
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& CCFG_SET_BITS(SET_MODE_CONF_VDDR_CAP,
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CCFG_MODE_CONF_VDDR_CAP_s,
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CCFG_MODE_CONF_VDDR_CAP_m),
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/* reserved for "future use" by Texas Instruments */
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.VOLT_LOAD_0 = 0xFFFFFFFF,
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.VOLT_LOAD_1 = 0xFFFFFFFF,
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.RTC_OFFSET = 0xFFFFFFFF,
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.FREQ_OFFSET = 0xFFFFFFFF,
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/* IEEE 802.15.4g MAC address */
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.IEEE_MAC_0 = 0xFFFFFFFF,
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.IEEE_MAC_1 = 0xFFFFFFFF,
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/* BLE MAC address */
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.IEEE_BLE_0 = 0xFFFFFFFF,
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.IEEE_BLE_1 = 0xFFFFFFFF,
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/* bootloader */
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.BL_CONFIG = CCFG_SET_BITS(SET_BL_CONFIG_BOOTLOADER_ENABLE,
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CCFG_BL_CONFIG_BOOTLOADER_ENABLE_s,
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CCFG_BL_CONFIG_BOOTLOADER_ENABLE_m)
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& CCFG_SET_BITS(SET_BL_CONFIG_BL_LEVEL,
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CCFG_BL_CONFIG_BL_LEVEL_s,
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CCFG_BL_CONFIG_BL_LEVEL_m)
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& CCFG_SET_BITS(SET_BL_CONFIG_BL_PIN_NUMBER,
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CCFG_BL_CONFIG_BL_PIN_NUMBER_s,
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CCFG_BL_CONFIG_BL_PIN_NUMBER_m)
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& CCFG_SET_BITS(SET_BL_CONFIG_BL_ENABLE,
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CCFG_BL_CONFIG_BL_ENABLE_s,
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CCFG_BL_CONFIG_BL_ENABLE_m),
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.ERASE_CONF = 0xFFFFFFFF,
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/* debugging */
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.CCFG_TI_OPTIONS = 0xFFFFFF00,
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.CCFG_TAP_DAP_0 = CCFG_SET_BITS(SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE,
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CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_s,
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CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_m)
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& CCFG_SET_BITS(SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE,
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CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_s,
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CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_m)
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& CCFG_SET_BITS(SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE,
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CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_s,
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CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_m),
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/* PBIST2, PBIST1 and AON disabled by default */
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.CCFG_TAP_DAP_1 = 0xFF000000,
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/* flash image vector table */
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.IMAGE_VALID_CONF = (reg32_t)&cortex_vector_base,
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/* flash sector write protections */
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.CCFG_PROT_31_0 = 0xFFFFFFFF,
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.CCFG_PROT_63_32 = 0xFFFFFFFF,
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.CCFG_PROT_95_64 = 0xFFFFFFFF,
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.CCFG_PROT_127_96 = 0xFFFFFFFF,
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};
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#endif /* IS_USED(CONFIG_CC26XX_CC13XX_UPDATE_CCFG) */
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/** @} */
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