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1045 lines
52 KiB
C
1045 lines
52 KiB
C
/******************************************************************************
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* Filename: hw_uart_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_UART_H__
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#define __HW_UART_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// UART component
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//
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//*****************************************************************************
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// Data
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#define UART_O_DR 0x00000000
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// Status
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#define UART_O_RSR 0x00000004
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// Error Clear
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#define UART_O_ECR 0x00000004
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// Flag
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#define UART_O_FR 0x00000018
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// Integer Baud-Rate Divisor
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#define UART_O_IBRD 0x00000024
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// Fractional Baud-Rate Divisor
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#define UART_O_FBRD 0x00000028
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// Line Control
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#define UART_O_LCRH 0x0000002C
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// Control
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#define UART_O_CTL 0x00000030
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// Interrupt FIFO Level Select
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#define UART_O_IFLS 0x00000034
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// Interrupt Mask Set/Clear
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#define UART_O_IMSC 0x00000038
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// Raw Interrupt Status
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#define UART_O_RIS 0x0000003C
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// Masked Interrupt Status
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#define UART_O_MIS 0x00000040
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// Interrupt Clear
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#define UART_O_ICR 0x00000044
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// DMA Control
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#define UART_O_DMACTL 0x00000048
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//*****************************************************************************
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//
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// Register: UART_O_DR
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//
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//*****************************************************************************
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// Field: [11] OE
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//
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// UART Overrun Error:
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// This bit is set to 1 if data is received and the receive FIFO is already
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// full. The FIFO contents remain valid because no more data is written when
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// the FIFO is full, , only the contents of the shift register are overwritten.
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// This is cleared to 0 once there is an empty space in the FIFO and a new
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// character can be written to it.
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#define UART_DR_OE 0x00000800
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#define UART_DR_OE_BITN 11
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#define UART_DR_OE_M 0x00000800
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#define UART_DR_OE_S 11
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// Field: [10] BE
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//
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// UART Break Error:
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// This bit is set to 1 if a break condition was detected, indicating that the
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// received data input (UARTRXD input pin) was held LOW for longer than a
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// full-word transmission time (defined as start, data, parity and stop bits).
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// In FIFO mode, this error is associated with the character at the top of the
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// FIFO (i.e., the oldest received data character since last read). When a
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// break occurs, a 0 character is loaded into the FIFO. The next character is
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// enabled after the receive data input (UARTRXD input pin) goes to a 1
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// (marking state), and the next valid start bit is received.
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#define UART_DR_BE 0x00000400
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#define UART_DR_BE_BITN 10
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#define UART_DR_BE_M 0x00000400
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#define UART_DR_BE_S 10
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// Field: [9] PE
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//
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// UART Parity Error:
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// When set to 1, it indicates that the parity of the received data character
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// does not match the parity that the LCRH.EPS and LCRH.SPS select.
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// In FIFO mode, this error is associated with the character at the top of the
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// FIFO (i.e., the oldest received data character since last read).
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#define UART_DR_PE 0x00000200
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#define UART_DR_PE_BITN 9
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#define UART_DR_PE_M 0x00000200
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#define UART_DR_PE_S 9
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// Field: [8] FE
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//
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// UART Framing Error:
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// When set to 1, it indicates that the received character did not have a valid
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// stop bit (a valid stop bit is 1).
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// In FIFO mode, this error is associated with the character at the top of the
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// FIFO (i.e., the oldest received data character since last read).
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#define UART_DR_FE 0x00000100
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#define UART_DR_FE_BITN 8
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#define UART_DR_FE_M 0x00000100
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#define UART_DR_FE_S 8
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// Field: [7:0] DATA
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//
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// Data transmitted or received:
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// On writes, the transmit data character is pushed into the FIFO.
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// On reads, the oldest received data character since the last read is
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// returned.
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#define UART_DR_DATA_W 8
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#define UART_DR_DATA_M 0x000000FF
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#define UART_DR_DATA_S 0
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//*****************************************************************************
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//
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// Register: UART_O_RSR
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//
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//*****************************************************************************
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// Field: [3] OE
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//
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// UART Overrun Error:
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// This bit is set to 1 if data is received and the receive FIFO is already
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// full. The FIFO contents remain valid because no more data is written when
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// the FIFO is full, , only the contents of the shift register are overwritten.
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// This is cleared to 0 once there is an empty space in the FIFO and a new
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// character can be written to it.
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#define UART_RSR_OE 0x00000008
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#define UART_RSR_OE_BITN 3
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#define UART_RSR_OE_M 0x00000008
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#define UART_RSR_OE_S 3
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// Field: [2] BE
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//
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// UART Break Error:
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// This bit is set to 1 if a break condition was detected, indicating that the
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// received data input (UARTRXD input pin) was held LOW for longer than a
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// full-word transmission time (defined as start, data, parity and stop bits).
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// When a break occurs, a 0 character is loaded into the FIFO. The next
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// character is enabled after the receive data input (UARTRXD input pin) goes
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// to a 1 (marking state), and the next valid start bit is received.
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#define UART_RSR_BE 0x00000004
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#define UART_RSR_BE_BITN 2
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#define UART_RSR_BE_M 0x00000004
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#define UART_RSR_BE_S 2
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// Field: [1] PE
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//
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// UART Parity Error:
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// When set to 1, it indicates that the parity of the received data character
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// does not match the parity that the LCRH.EPS and LCRH.SPS select.
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#define UART_RSR_PE 0x00000002
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#define UART_RSR_PE_BITN 1
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#define UART_RSR_PE_M 0x00000002
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#define UART_RSR_PE_S 1
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// Field: [0] FE
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//
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// UART Framing Error:
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// When set to 1, it indicates that the received character did not have a valid
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// stop bit (a valid stop bit is 1).
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#define UART_RSR_FE 0x00000001
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#define UART_RSR_FE_BITN 0
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#define UART_RSR_FE_M 0x00000001
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#define UART_RSR_FE_S 0
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//*****************************************************************************
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//
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// Register: UART_O_ECR
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//
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//*****************************************************************************
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// Field: [3] OE
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//
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// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are
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// cleared to 0 by any write to this register.
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#define UART_ECR_OE 0x00000008
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#define UART_ECR_OE_BITN 3
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#define UART_ECR_OE_M 0x00000008
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#define UART_ECR_OE_S 3
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// Field: [2] BE
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//
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// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are
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// cleared to 0 by any write to this register.
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#define UART_ECR_BE 0x00000004
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#define UART_ECR_BE_BITN 2
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#define UART_ECR_BE_M 0x00000004
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#define UART_ECR_BE_S 2
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// Field: [1] PE
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//
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// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are
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// cleared to 0 by any write to this register.
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#define UART_ECR_PE 0x00000002
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#define UART_ECR_PE_BITN 1
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#define UART_ECR_PE_M 0x00000002
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#define UART_ECR_PE_S 1
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// Field: [0] FE
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//
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// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are
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// cleared to 0 by any write to this register.
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#define UART_ECR_FE 0x00000001
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#define UART_ECR_FE_BITN 0
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#define UART_ECR_FE_M 0x00000001
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#define UART_ECR_FE_S 0
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//*****************************************************************************
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//
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// Register: UART_O_FR
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//
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//*****************************************************************************
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// Field: [7] TXFE
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//
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// UART Transmit FIFO Empty:
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// The meaning of this bit depends on the state of LCRH.FEN .
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// - If the FIFO is disabled, this bit is set when the transmit holding
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// register is empty.
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// - If the FIFO is enabled, this bit is set when the transmit FIFO is empty.
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// This bit does not indicate if there is data in the transmit shift register.
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#define UART_FR_TXFE 0x00000080
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#define UART_FR_TXFE_BITN 7
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#define UART_FR_TXFE_M 0x00000080
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#define UART_FR_TXFE_S 7
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// Field: [6] RXFF
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//
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// UART Receive FIFO Full:
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// The meaning of this bit depends on the state of LCRH.FEN.
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// - If the FIFO is disabled, this bit is set when the receive holding
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// register is full.
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// - If the FIFO is enabled, this bit is set when the receive FIFO is full.
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#define UART_FR_RXFF 0x00000040
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#define UART_FR_RXFF_BITN 6
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#define UART_FR_RXFF_M 0x00000040
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#define UART_FR_RXFF_S 6
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// Field: [5] TXFF
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//
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// UART Transmit FIFO Full:
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// Transmit FIFO full. The meaning of this bit depends on the state of
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// LCRH.FEN.
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// - If the FIFO is disabled, this bit is set when the transmit holding
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// register is full.
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// - If the FIFO is enabled, this bit is set when the transmit FIFO is full.
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#define UART_FR_TXFF 0x00000020
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#define UART_FR_TXFF_BITN 5
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#define UART_FR_TXFF_M 0x00000020
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#define UART_FR_TXFF_S 5
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// Field: [4] RXFE
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//
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// UART Receive FIFO Empty:
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// Receive FIFO empty. The meaning of this bit depends on the state of
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// LCRH.FEN.
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// - If the FIFO is disabled, this bit is set when the receive holding
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// register is empty.
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// - If the FIFO is enabled, this bit is set when the receive FIFO is empty.
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#define UART_FR_RXFE 0x00000010
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#define UART_FR_RXFE_BITN 4
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#define UART_FR_RXFE_M 0x00000010
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#define UART_FR_RXFE_S 4
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// Field: [3] BUSY
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//
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// UART Busy:
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// If this bit is set to 1, the UART is busy transmitting data. This bit
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// remains set until the complete byte, including all the stop bits, has been
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// sent from the shift register.
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// This bit is set as soon as the transmit FIFO becomes non-empty, regardless
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// of whether the UART is enabled or not.
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#define UART_FR_BUSY 0x00000008
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#define UART_FR_BUSY_BITN 3
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#define UART_FR_BUSY_M 0x00000008
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#define UART_FR_BUSY_S 3
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// Field: [0] CTS
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//
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// Clear To Send:
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// This bit is the complement of the active-low UART CTS input pin.
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// That is, the bit is 1 when CTS input pin is LOW.
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#define UART_FR_CTS 0x00000001
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#define UART_FR_CTS_BITN 0
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#define UART_FR_CTS_M 0x00000001
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#define UART_FR_CTS_S 0
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//*****************************************************************************
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//
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// Register: UART_O_IBRD
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//
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//*****************************************************************************
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// Field: [15:0] DIVINT
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//
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// The integer baud rate divisor:
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// The baud rate divisor is calculated using the formula below:
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// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)
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// Baud rate divisor must be minimum 1 and maximum 65535.
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// That is, DIVINT=0 does not give a valid baud rate.
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// Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be
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// illegal.
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// A valid value must be written to this field before the UART can be used for
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// RX or TX operations.
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#define UART_IBRD_DIVINT_W 16
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#define UART_IBRD_DIVINT_M 0x0000FFFF
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#define UART_IBRD_DIVINT_S 0
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//*****************************************************************************
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//
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// Register: UART_O_FBRD
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//
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//*****************************************************************************
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// Field: [5:0] DIVFRAC
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//
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// Fractional Baud-Rate Divisor:
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// The baud rate divisor is calculated using the formula below:
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// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)
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// Baud rate divisor must be minimum 1 and maximum 65535.
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// That is, IBRD.DIVINT=0 does not give a valid baud rate.
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// Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be
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// illegal.
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// A valid value must be written to this field before the UART can be used for
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// RX or TX operations.
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#define UART_FBRD_DIVFRAC_W 6
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#define UART_FBRD_DIVFRAC_M 0x0000003F
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#define UART_FBRD_DIVFRAC_S 0
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//*****************************************************************************
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//
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// Register: UART_O_LCRH
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//
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//*****************************************************************************
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// Field: [7] SPS
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//
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// UART Stick Parity Select:
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//
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// 0: Stick parity is disabled
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// 1: The parity bit is transmitted and checked as invert of EPS field (i.e.
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// the parity bit is transmitted and checked as 1 when EPS = 0).
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//
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// This bit has no effect when PEN disables parity checking and generation.
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#define UART_LCRH_SPS 0x00000080
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#define UART_LCRH_SPS_BITN 7
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#define UART_LCRH_SPS_M 0x00000080
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#define UART_LCRH_SPS_S 7
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// Field: [6:5] WLEN
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//
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// UART Word Length:
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// These bits indicate the number of data bits transmitted or received in a
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// frame.
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// ENUMs:
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// 8 Word Length 8 bits
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// 7 Word Length 7 bits
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// 6 Word Length 6 bits
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// 5 Word Length 5 bits
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#define UART_LCRH_WLEN_W 2
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#define UART_LCRH_WLEN_M 0x00000060
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#define UART_LCRH_WLEN_S 5
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#define UART_LCRH_WLEN_8 0x00000060
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#define UART_LCRH_WLEN_7 0x00000040
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#define UART_LCRH_WLEN_6 0x00000020
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#define UART_LCRH_WLEN_5 0x00000000
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// Field: [4] FEN
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//
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// UART Enable FIFOs
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// ENUMs:
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// EN Transmit and receive FIFO buffers are enabled
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// (FIFO mode)
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// DIS FIFOs are disabled (character mode) that is, the
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// FIFOs become 1-byte-deep holding registers.
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#define UART_LCRH_FEN 0x00000010
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#define UART_LCRH_FEN_BITN 4
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#define UART_LCRH_FEN_M 0x00000010
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#define UART_LCRH_FEN_S 4
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#define UART_LCRH_FEN_EN 0x00000010
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#define UART_LCRH_FEN_DIS 0x00000000
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// Field: [3] STP2
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//
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// UART Two Stop Bits Select:
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// If this bit is set to 1, two stop bits are transmitted at the end of the
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// frame. The receive logic does not check for two stop bits being received.
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#define UART_LCRH_STP2 0x00000008
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#define UART_LCRH_STP2_BITN 3
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#define UART_LCRH_STP2_M 0x00000008
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#define UART_LCRH_STP2_S 3
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// Field: [2] EPS
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//
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// UART Even Parity Select
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// ENUMs:
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// EVEN Even parity: The UART generates or checks for an
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// even number of 1s in the data and parity bits.
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// ODD Odd parity: The UART generates or checks for an
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// odd number of 1s in the data and parity bits.
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#define UART_LCRH_EPS 0x00000004
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#define UART_LCRH_EPS_BITN 2
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#define UART_LCRH_EPS_M 0x00000004
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#define UART_LCRH_EPS_S 2
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#define UART_LCRH_EPS_EVEN 0x00000004
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#define UART_LCRH_EPS_ODD 0x00000000
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// Field: [1] PEN
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//
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// UART Parity Enable
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// This bit controls generation and checking of parity bit.
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// ENUMs:
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// EN Parity checking and generation is enabled.
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// DIS Parity is disabled and no parity bit is added to
|
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// the data frame
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#define UART_LCRH_PEN 0x00000002
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#define UART_LCRH_PEN_BITN 1
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#define UART_LCRH_PEN_M 0x00000002
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#define UART_LCRH_PEN_S 1
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#define UART_LCRH_PEN_EN 0x00000002
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#define UART_LCRH_PEN_DIS 0x00000000
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// Field: [0] BRK
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//
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// UART Send Break
|
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// If this bit is set to 1, a low-level is continually output on the UARTTXD
|
|
// output pin, after completing transmission of the current character. For the
|
|
// proper execution of the break command, the
|
|
// software must set this bit for at least two complete frames. For normal use,
|
|
// this bit must be cleared to 0.
|
|
#define UART_LCRH_BRK 0x00000001
|
|
#define UART_LCRH_BRK_BITN 0
|
|
#define UART_LCRH_BRK_M 0x00000001
|
|
#define UART_LCRH_BRK_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: UART_O_CTL
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [15] CTSEN
|
|
//
|
|
// CTS hardware flow control enable
|
|
// ENUMs:
|
|
// EN CTS hardware flow control enabled
|
|
// DIS CTS hardware flow control disabled
|
|
#define UART_CTL_CTSEN 0x00008000
|
|
#define UART_CTL_CTSEN_BITN 15
|
|
#define UART_CTL_CTSEN_M 0x00008000
|
|
#define UART_CTL_CTSEN_S 15
|
|
#define UART_CTL_CTSEN_EN 0x00008000
|
|
#define UART_CTL_CTSEN_DIS 0x00000000
|
|
|
|
// Field: [14] RTSEN
|
|
//
|
|
// RTS hardware flow control enable
|
|
// ENUMs:
|
|
// EN RTS hardware flow control enabled
|
|
// DIS RTS hardware flow control disabled
|
|
#define UART_CTL_RTSEN 0x00004000
|
|
#define UART_CTL_RTSEN_BITN 14
|
|
#define UART_CTL_RTSEN_M 0x00004000
|
|
#define UART_CTL_RTSEN_S 14
|
|
#define UART_CTL_RTSEN_EN 0x00004000
|
|
#define UART_CTL_RTSEN_DIS 0x00000000
|
|
|
|
// Field: [11] RTS
|
|
//
|
|
// Request to Send
|
|
// This bit is the complement of the active-low UART RTS output. That is, when
|
|
// the bit is programmed to a 1 then RTS output on the pins is LOW.
|
|
#define UART_CTL_RTS 0x00000800
|
|
#define UART_CTL_RTS_BITN 11
|
|
#define UART_CTL_RTS_M 0x00000800
|
|
#define UART_CTL_RTS_S 11
|
|
|
|
// Field: [9] RXE
|
|
//
|
|
// UART Receive Enable
|
|
// If the UART is disabled in the middle of reception, it completes the current
|
|
// character before stopping.
|
|
// ENUMs:
|
|
// EN UART Receive enabled
|
|
// DIS UART Receive disabled
|
|
#define UART_CTL_RXE 0x00000200
|
|
#define UART_CTL_RXE_BITN 9
|
|
#define UART_CTL_RXE_M 0x00000200
|
|
#define UART_CTL_RXE_S 9
|
|
#define UART_CTL_RXE_EN 0x00000200
|
|
#define UART_CTL_RXE_DIS 0x00000000
|
|
|
|
// Field: [8] TXE
|
|
//
|
|
// UART Transmit Enable
|
|
// If the UART is disabled in the middle of transmission, it completes the
|
|
// current character before stopping.
|
|
// ENUMs:
|
|
// EN UART Transmit enabled
|
|
// DIS UART Transmit disabled
|
|
#define UART_CTL_TXE 0x00000100
|
|
#define UART_CTL_TXE_BITN 8
|
|
#define UART_CTL_TXE_M 0x00000100
|
|
#define UART_CTL_TXE_S 8
|
|
#define UART_CTL_TXE_EN 0x00000100
|
|
#define UART_CTL_TXE_DIS 0x00000000
|
|
|
|
// Field: [7] LBE
|
|
//
|
|
// UART Loop Back Enable:
|
|
// Enabling the loop-back mode connects the UARTTXD output from the UART to
|
|
// UARTRXD input of the UART.
|
|
// ENUMs:
|
|
// EN Loop Back enabled
|
|
// DIS Loop Back disabled
|
|
#define UART_CTL_LBE 0x00000080
|
|
#define UART_CTL_LBE_BITN 7
|
|
#define UART_CTL_LBE_M 0x00000080
|
|
#define UART_CTL_LBE_S 7
|
|
#define UART_CTL_LBE_EN 0x00000080
|
|
#define UART_CTL_LBE_DIS 0x00000000
|
|
|
|
// Field: [0] UARTEN
|
|
//
|
|
// UART Enable
|
|
// ENUMs:
|
|
// EN UART enabled
|
|
// DIS UART disabled
|
|
#define UART_CTL_UARTEN 0x00000001
|
|
#define UART_CTL_UARTEN_BITN 0
|
|
#define UART_CTL_UARTEN_M 0x00000001
|
|
#define UART_CTL_UARTEN_S 0
|
|
#define UART_CTL_UARTEN_EN 0x00000001
|
|
#define UART_CTL_UARTEN_DIS 0x00000000
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: UART_O_IFLS
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [5:3] RXSEL
|
|
//
|
|
// Receive interrupt FIFO level select:
|
|
// This field sets the trigger points for the receive interrupt. Values
|
|
// 0b101-0b111 are reserved.
|
|
// ENUMs:
|
|
// 7_8 Receive FIFO becomes >= 7/8 full
|
|
// 6_8 Receive FIFO becomes >= 3/4 full
|
|
// 4_8 Receive FIFO becomes >= 1/2 full
|
|
// 2_8 Receive FIFO becomes >= 1/4 full
|
|
// 1_8 Receive FIFO becomes >= 1/8 full
|
|
#define UART_IFLS_RXSEL_W 3
|
|
#define UART_IFLS_RXSEL_M 0x00000038
|
|
#define UART_IFLS_RXSEL_S 3
|
|
#define UART_IFLS_RXSEL_7_8 0x00000020
|
|
#define UART_IFLS_RXSEL_6_8 0x00000018
|
|
#define UART_IFLS_RXSEL_4_8 0x00000010
|
|
#define UART_IFLS_RXSEL_2_8 0x00000008
|
|
#define UART_IFLS_RXSEL_1_8 0x00000000
|
|
|
|
// Field: [2:0] TXSEL
|
|
//
|
|
// Transmit interrupt FIFO level select:
|
|
// This field sets the trigger points for the transmit interrupt. Values
|
|
// 0b101-0b111 are reserved.
|
|
// ENUMs:
|
|
// 7_8 Transmit FIFO becomes <= 7/8 full
|
|
// 6_8 Transmit FIFO becomes <= 3/4 full
|
|
// 4_8 Transmit FIFO becomes <= 1/2 full
|
|
// 2_8 Transmit FIFO becomes <= 1/4 full
|
|
// 1_8 Transmit FIFO becomes <= 1/8 full
|
|
#define UART_IFLS_TXSEL_W 3
|
|
#define UART_IFLS_TXSEL_M 0x00000007
|
|
#define UART_IFLS_TXSEL_S 0
|
|
#define UART_IFLS_TXSEL_7_8 0x00000004
|
|
#define UART_IFLS_TXSEL_6_8 0x00000003
|
|
#define UART_IFLS_TXSEL_4_8 0x00000002
|
|
#define UART_IFLS_TXSEL_2_8 0x00000001
|
|
#define UART_IFLS_TXSEL_1_8 0x00000000
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: UART_O_IMSC
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [10] OEIM
|
|
//
|
|
// Overrun error interrupt mask. A read returns the current mask for UART's
|
|
// overrun error interrupt. On a write of 1, the mask of the overrun error
|
|
// interrupt is set which means the interrupt state will be reflected in
|
|
// MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not
|
|
// reflect the interrupt.
|
|
#define UART_IMSC_OEIM 0x00000400
|
|
#define UART_IMSC_OEIM_BITN 10
|
|
#define UART_IMSC_OEIM_M 0x00000400
|
|
#define UART_IMSC_OEIM_S 10
|
|
|
|
// Field: [9] BEIM
|
|
//
|
|
// Break error interrupt mask. A read returns the current mask for UART's break
|
|
// error interrupt. On a write of 1, the mask of the overrun error interrupt is
|
|
// set which means the interrupt state will be reflected in MIS.BEMIS. A write
|
|
// of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt.
|
|
#define UART_IMSC_BEIM 0x00000200
|
|
#define UART_IMSC_BEIM_BITN 9
|
|
#define UART_IMSC_BEIM_M 0x00000200
|
|
#define UART_IMSC_BEIM_S 9
|
|
|
|
// Field: [8] PEIM
|
|
//
|
|
// Parity error interrupt mask. A read returns the current mask for UART's
|
|
// parity error interrupt. On a write of 1, the mask of the overrun error
|
|
// interrupt is set which means the interrupt state will be reflected in
|
|
// MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not
|
|
// reflect the interrupt.
|
|
#define UART_IMSC_PEIM 0x00000100
|
|
#define UART_IMSC_PEIM_BITN 8
|
|
#define UART_IMSC_PEIM_M 0x00000100
|
|
#define UART_IMSC_PEIM_S 8
|
|
|
|
// Field: [7] FEIM
|
|
//
|
|
// Framing error interrupt mask. A read returns the current mask for UART's
|
|
// framing error interrupt. On a write of 1, the mask of the overrun error
|
|
// interrupt is set which means the interrupt state will be reflected in
|
|
// MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not
|
|
// reflect the interrupt.
|
|
#define UART_IMSC_FEIM 0x00000080
|
|
#define UART_IMSC_FEIM_BITN 7
|
|
#define UART_IMSC_FEIM_M 0x00000080
|
|
#define UART_IMSC_FEIM_S 7
|
|
|
|
// Field: [6] RTIM
|
|
//
|
|
// Receive timeout interrupt mask. A read returns the current mask for UART's
|
|
// receive timeout interrupt. On a write of 1, the mask of the overrun error
|
|
// interrupt is set which means the interrupt state will be reflected in
|
|
// MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not
|
|
// reflect the interrupt.
|
|
// The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the
|
|
// mask is set (RTIM = 1). This is because the mask acts as an enable for power
|
|
// saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS.
|
|
#define UART_IMSC_RTIM 0x00000040
|
|
#define UART_IMSC_RTIM_BITN 6
|
|
#define UART_IMSC_RTIM_M 0x00000040
|
|
#define UART_IMSC_RTIM_S 6
|
|
|
|
// Field: [5] TXIM
|
|
//
|
|
// Transmit interrupt mask. A read returns the current mask for UART's transmit
|
|
// interrupt. On a write of 1, the mask of the overrun error interrupt is set
|
|
// which means the interrupt state will be reflected in MIS.TXMIS. A write of 0
|
|
// clears the mask which means MIS.TXMIS will not reflect the interrupt.
|
|
#define UART_IMSC_TXIM 0x00000020
|
|
#define UART_IMSC_TXIM_BITN 5
|
|
#define UART_IMSC_TXIM_M 0x00000020
|
|
#define UART_IMSC_TXIM_S 5
|
|
|
|
// Field: [4] RXIM
|
|
//
|
|
// Receive interrupt mask. A read returns the current mask for UART's receive
|
|
// interrupt. On a write of 1, the mask of the overrun error interrupt is set
|
|
// which means the interrupt state will be reflected in MIS.RXMIS. A write of 0
|
|
// clears the mask which means MIS.RXMIS will not reflect the interrupt.
|
|
#define UART_IMSC_RXIM 0x00000010
|
|
#define UART_IMSC_RXIM_BITN 4
|
|
#define UART_IMSC_RXIM_M 0x00000010
|
|
#define UART_IMSC_RXIM_S 4
|
|
|
|
// Field: [1] CTSMIM
|
|
//
|
|
// Clear to Send (CTS) modem interrupt mask. A read returns the current mask
|
|
// for UART's clear to send interrupt. On a write of 1, the mask of the overrun
|
|
// error interrupt is set which means the interrupt state will be reflected in
|
|
// MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not
|
|
// reflect the interrupt.
|
|
#define UART_IMSC_CTSMIM 0x00000002
|
|
#define UART_IMSC_CTSMIM_BITN 1
|
|
#define UART_IMSC_CTSMIM_M 0x00000002
|
|
#define UART_IMSC_CTSMIM_S 1
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: UART_O_RIS
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [10] OERIS
|
|
//
|
|
// Overrun error interrupt status:
|
|
// This field returns the raw interrupt state of UART's overrun error
|
|
// interrupt. Overrun error occurs if data is received and the receive FIFO is
|
|
// full.
|
|
#define UART_RIS_OERIS 0x00000400
|
|
#define UART_RIS_OERIS_BITN 10
|
|
#define UART_RIS_OERIS_M 0x00000400
|
|
#define UART_RIS_OERIS_S 10
|
|
|
|
// Field: [9] BERIS
|
|
//
|
|
// Break error interrupt status:
|
|
// This field returns the raw interrupt state of UART's break error interrupt.
|
|
// Break error is set when a break condition is detected, indicating that the
|
|
// received data input (UARTRXD input pin) was held LOW for longer than a
|
|
// full-word transmission time (defined as start, data, parity and stop bits).
|
|
#define UART_RIS_BERIS 0x00000200
|
|
#define UART_RIS_BERIS_BITN 9
|
|
#define UART_RIS_BERIS_M 0x00000200
|
|
#define UART_RIS_BERIS_S 9
|
|
|
|
// Field: [8] PERIS
|
|
//
|
|
// Parity error interrupt status:
|
|
// This field returns the raw interrupt state of UART's parity error interrupt.
|
|
// Parity error is set if the parity of the received data character does not
|
|
// match the parity that the LCRH.EPS and LCRH.SPS select.
|
|
#define UART_RIS_PERIS 0x00000100
|
|
#define UART_RIS_PERIS_BITN 8
|
|
#define UART_RIS_PERIS_M 0x00000100
|
|
#define UART_RIS_PERIS_S 8
|
|
|
|
// Field: [7] FERIS
|
|
//
|
|
// Framing error interrupt status:
|
|
// This field returns the raw interrupt state of UART's framing error
|
|
// interrupt. Framing error is set if the received character does not have a
|
|
// valid stop bit (a valid stop bit is 1).
|
|
#define UART_RIS_FERIS 0x00000080
|
|
#define UART_RIS_FERIS_BITN 7
|
|
#define UART_RIS_FERIS_M 0x00000080
|
|
#define UART_RIS_FERIS_S 7
|
|
|
|
// Field: [6] RTRIS
|
|
//
|
|
// Receive timeout interrupt status:
|
|
// This field returns the raw interrupt state of UART's receive timeout
|
|
// interrupt. The receive timeout interrupt is asserted when the receive FIFO
|
|
// is not empty, and no more data is received during a 32-bit period. The
|
|
// receive timeout interrupt is cleared either when the FIFO becomes empty
|
|
// through reading all the data, or when a 1 is written to ICR.RTIC.
|
|
// The raw interrupt for receive timeout cannot be set unless the mask is set
|
|
// (IMSC.RTIM = 1). This is because the mask acts as an enable for power
|
|
// saving. That is, the same status can be read from MIS.RTMIS and RTRIS.
|
|
#define UART_RIS_RTRIS 0x00000040
|
|
#define UART_RIS_RTRIS_BITN 6
|
|
#define UART_RIS_RTRIS_M 0x00000040
|
|
#define UART_RIS_RTRIS_S 6
|
|
|
|
// Field: [5] TXRIS
|
|
//
|
|
// Transmit interrupt status:
|
|
// This field returns the raw interrupt state of UART's transmit interrupt.
|
|
// When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if
|
|
// the number of bytes in transmit FIFO is equal to or lower than the
|
|
// programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by
|
|
// writing data to the transmit FIFO until it becomes greater than the trigger
|
|
// level, or by clearing the interrupt through ICR.TXIC.
|
|
// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one
|
|
// location, the transmit interrupt is asserted if there is no data present in
|
|
// the transmitters single location. It is cleared by performing a single write
|
|
// to the transmit FIFO, or by clearing the interrupt through ICR.TXIC.
|
|
#define UART_RIS_TXRIS 0x00000020
|
|
#define UART_RIS_TXRIS_BITN 5
|
|
#define UART_RIS_TXRIS_M 0x00000020
|
|
#define UART_RIS_TXRIS_S 5
|
|
|
|
// Field: [4] RXRIS
|
|
//
|
|
// Receive interrupt status:
|
|
// This field returns the raw interrupt state of UART's receive interrupt.
|
|
// When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if
|
|
// the receive FIFO reaches the programmed trigger
|
|
// level (IFLS.RXSEL). The receive interrupt is cleared by reading data from
|
|
// the receive FIFO until it becomes less than the trigger level, or by
|
|
// clearing the interrupt through ICR.RXIC.
|
|
// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one
|
|
// location, the receive interrupt is asserted if data is received
|
|
// thereby filling the location. The receive interrupt is cleared by performing
|
|
// a single read of the receive FIFO, or by clearing the interrupt through
|
|
// ICR.RXIC.
|
|
#define UART_RIS_RXRIS 0x00000010
|
|
#define UART_RIS_RXRIS_BITN 4
|
|
#define UART_RIS_RXRIS_M 0x00000010
|
|
#define UART_RIS_RXRIS_S 4
|
|
|
|
// Field: [1] CTSRMIS
|
|
//
|
|
// Clear to Send (CTS) modem interrupt status:
|
|
// This field returns the raw interrupt state of UART's clear to send
|
|
// interrupt.
|
|
#define UART_RIS_CTSRMIS 0x00000002
|
|
#define UART_RIS_CTSRMIS_BITN 1
|
|
#define UART_RIS_CTSRMIS_M 0x00000002
|
|
#define UART_RIS_CTSRMIS_S 1
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: UART_O_MIS
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [10] OEMIS
|
|
//
|
|
// Overrun error masked interrupt status:
|
|
// This field returns the masked interrupt state of the overrun interrupt which
|
|
// is the AND product of raw interrupt state RIS.OERIS and the mask setting
|
|
// IMSC.OEIM.
|
|
#define UART_MIS_OEMIS 0x00000400
|
|
#define UART_MIS_OEMIS_BITN 10
|
|
#define UART_MIS_OEMIS_M 0x00000400
|
|
#define UART_MIS_OEMIS_S 10
|
|
|
|
// Field: [9] BEMIS
|
|
//
|
|
// Break error masked interrupt status:
|
|
// This field returns the masked interrupt state of the break error interrupt
|
|
// which is the AND product of raw interrupt state RIS.BERIS and the mask
|
|
// setting IMSC.BEIM.
|
|
#define UART_MIS_BEMIS 0x00000200
|
|
#define UART_MIS_BEMIS_BITN 9
|
|
#define UART_MIS_BEMIS_M 0x00000200
|
|
#define UART_MIS_BEMIS_S 9
|
|
|
|
// Field: [8] PEMIS
|
|
//
|
|
// Parity error masked interrupt status:
|
|
// This field returns the masked interrupt state of the parity error interrupt
|
|
// which is the AND product of raw interrupt state RIS.PERIS and the mask
|
|
// setting IMSC.PEIM.
|
|
#define UART_MIS_PEMIS 0x00000100
|
|
#define UART_MIS_PEMIS_BITN 8
|
|
#define UART_MIS_PEMIS_M 0x00000100
|
|
#define UART_MIS_PEMIS_S 8
|
|
|
|
// Field: [7] FEMIS
|
|
//
|
|
// Framing error masked interrupt status: Returns the masked interrupt state of
|
|
// the framing error interrupt which is the AND product of raw interrupt state
|
|
// RIS.FERIS and the mask setting IMSC.FEIM.
|
|
#define UART_MIS_FEMIS 0x00000080
|
|
#define UART_MIS_FEMIS_BITN 7
|
|
#define UART_MIS_FEMIS_M 0x00000080
|
|
#define UART_MIS_FEMIS_S 7
|
|
|
|
// Field: [6] RTMIS
|
|
//
|
|
// Receive timeout masked interrupt status:
|
|
// Returns the masked interrupt state of the receive timeout interrupt.
|
|
// The raw interrupt for receive timeout cannot be set unless the mask is set
|
|
// (IMSC.RTIM = 1). This is because the mask acts as an enable for power
|
|
// saving. That is, the same status can be read from RTMIS and RIS.RTRIS.
|
|
#define UART_MIS_RTMIS 0x00000040
|
|
#define UART_MIS_RTMIS_BITN 6
|
|
#define UART_MIS_RTMIS_M 0x00000040
|
|
#define UART_MIS_RTMIS_S 6
|
|
|
|
// Field: [5] TXMIS
|
|
//
|
|
// Transmit masked interrupt status:
|
|
// This field returns the masked interrupt state of the transmit interrupt
|
|
// which is the AND product of raw interrupt state RIS.TXRIS and the mask
|
|
// setting IMSC.TXIM.
|
|
#define UART_MIS_TXMIS 0x00000020
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#define UART_MIS_TXMIS_BITN 5
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#define UART_MIS_TXMIS_M 0x00000020
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#define UART_MIS_TXMIS_S 5
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// Field: [4] RXMIS
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//
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// Receive masked interrupt status:
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// This field returns the masked interrupt state of the receive interrupt
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// which is the AND product of raw interrupt state RIS.RXRIS and the mask
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// setting IMSC.RXIM.
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#define UART_MIS_RXMIS 0x00000010
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#define UART_MIS_RXMIS_BITN 4
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#define UART_MIS_RXMIS_M 0x00000010
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#define UART_MIS_RXMIS_S 4
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// Field: [1] CTSMMIS
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//
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// Clear to Send (CTS) modem masked interrupt status:
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// This field returns the masked interrupt state of the clear to send interrupt
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// which is the AND product of raw interrupt state RIS.CTSRMIS and the mask
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// setting IMSC.CTSMIM.
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#define UART_MIS_CTSMMIS 0x00000002
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#define UART_MIS_CTSMMIS_BITN 1
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#define UART_MIS_CTSMMIS_M 0x00000002
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#define UART_MIS_CTSMMIS_S 1
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//*****************************************************************************
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//
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// Register: UART_O_ICR
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//
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//*****************************************************************************
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// Field: [10] OEIC
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//
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// Overrun error interrupt clear:
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// Writing 1 to this field clears the overrun error interrupt (RIS.OERIS).
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// Writing 0 has no effect.
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#define UART_ICR_OEIC 0x00000400
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#define UART_ICR_OEIC_BITN 10
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#define UART_ICR_OEIC_M 0x00000400
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#define UART_ICR_OEIC_S 10
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// Field: [9] BEIC
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//
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// Break error interrupt clear:
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// Writing 1 to this field clears the break error interrupt (RIS.BERIS).
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// Writing 0 has no effect.
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#define UART_ICR_BEIC 0x00000200
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#define UART_ICR_BEIC_BITN 9
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#define UART_ICR_BEIC_M 0x00000200
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#define UART_ICR_BEIC_S 9
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|
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// Field: [8] PEIC
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//
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// Parity error interrupt clear:
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// Writing 1 to this field clears the parity error interrupt (RIS.PERIS).
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// Writing 0 has no effect.
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#define UART_ICR_PEIC 0x00000100
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#define UART_ICR_PEIC_BITN 8
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#define UART_ICR_PEIC_M 0x00000100
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#define UART_ICR_PEIC_S 8
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|
|
|
// Field: [7] FEIC
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//
|
|
// Framing error interrupt clear:
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// Writing 1 to this field clears the framing error interrupt (RIS.FERIS).
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|
// Writing 0 has no effect.
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#define UART_ICR_FEIC 0x00000080
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#define UART_ICR_FEIC_BITN 7
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#define UART_ICR_FEIC_M 0x00000080
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#define UART_ICR_FEIC_S 7
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|
|
|
// Field: [6] RTIC
|
|
//
|
|
// Receive timeout interrupt clear:
|
|
// Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS).
|
|
// Writing 0 has no effect.
|
|
#define UART_ICR_RTIC 0x00000040
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#define UART_ICR_RTIC_BITN 6
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#define UART_ICR_RTIC_M 0x00000040
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#define UART_ICR_RTIC_S 6
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|
|
|
// Field: [5] TXIC
|
|
//
|
|
// Transmit interrupt clear:
|
|
// Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0
|
|
// has no effect.
|
|
#define UART_ICR_TXIC 0x00000020
|
|
#define UART_ICR_TXIC_BITN 5
|
|
#define UART_ICR_TXIC_M 0x00000020
|
|
#define UART_ICR_TXIC_S 5
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|
|
|
// Field: [4] RXIC
|
|
//
|
|
// Receive interrupt clear:
|
|
// Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0
|
|
// has no effect.
|
|
#define UART_ICR_RXIC 0x00000010
|
|
#define UART_ICR_RXIC_BITN 4
|
|
#define UART_ICR_RXIC_M 0x00000010
|
|
#define UART_ICR_RXIC_S 4
|
|
|
|
// Field: [1] CTSMIC
|
|
//
|
|
// Clear to Send (CTS) modem interrupt clear:
|
|
// Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS).
|
|
// Writing 0 has no effect.
|
|
#define UART_ICR_CTSMIC 0x00000002
|
|
#define UART_ICR_CTSMIC_BITN 1
|
|
#define UART_ICR_CTSMIC_M 0x00000002
|
|
#define UART_ICR_CTSMIC_S 1
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: UART_O_DMACTL
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [2] DMAONERR
|
|
//
|
|
// DMA on error. If this bit is set to 1, the DMA receive request outputs (for
|
|
// single and burst requests) are disabled when the UART error interrupt is
|
|
// asserted (more specifically if any of the error interrupts RIS.PERIS,
|
|
// RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted).
|
|
#define UART_DMACTL_DMAONERR 0x00000004
|
|
#define UART_DMACTL_DMAONERR_BITN 2
|
|
#define UART_DMACTL_DMAONERR_M 0x00000004
|
|
#define UART_DMACTL_DMAONERR_S 2
|
|
|
|
// Field: [1] TXDMAE
|
|
//
|
|
// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is
|
|
// enabled.
|
|
#define UART_DMACTL_TXDMAE 0x00000002
|
|
#define UART_DMACTL_TXDMAE_BITN 1
|
|
#define UART_DMACTL_TXDMAE_M 0x00000002
|
|
#define UART_DMACTL_TXDMAE_S 1
|
|
|
|
// Field: [0] RXDMAE
|
|
//
|
|
// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is
|
|
// enabled.
|
|
#define UART_DMACTL_RXDMAE 0x00000001
|
|
#define UART_DMACTL_RXDMAE_BITN 0
|
|
#define UART_DMACTL_RXDMAE_M 0x00000001
|
|
#define UART_DMACTL_RXDMAE_S 0
|
|
|
|
|
|
#endif // __UART__
|