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154 lines
7.4 KiB
C
154 lines
7.4 KiB
C
/******************************************************************************
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* Filename: hw_rfc_pwr_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_RFC_PWR_H__
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#define __HW_RFC_PWR_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// RFC_PWR component
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//
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//*****************************************************************************
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// RF Core Power Management and Clock Enable
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#define RFC_PWR_O_PWMCLKEN 0x00000000
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//*****************************************************************************
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//
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// Register: RFC_PWR_O_PWMCLKEN
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//
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//*****************************************************************************
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// Field: [10] RFCTRC
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//
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// Enable clock to the RF Core Tracer (RFCTRC) module.
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#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400
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#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10
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#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400
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#define RFC_PWR_PWMCLKEN_RFCTRC_S 10
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// Field: [9] FSCA
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//
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// Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA)
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// module.
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#define RFC_PWR_PWMCLKEN_FSCA 0x00000200
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#define RFC_PWR_PWMCLKEN_FSCA_BITN 9
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#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200
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#define RFC_PWR_PWMCLKEN_FSCA_S 9
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// Field: [8] PHA
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//
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// Enable clock to the Packet Handling Accelerator (PHA) module.
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#define RFC_PWR_PWMCLKEN_PHA 0x00000100
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#define RFC_PWR_PWMCLKEN_PHA_BITN 8
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#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100
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#define RFC_PWR_PWMCLKEN_PHA_S 8
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// Field: [7] RAT
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//
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// Enable clock to the Radio Timer (RAT) module.
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#define RFC_PWR_PWMCLKEN_RAT 0x00000080
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#define RFC_PWR_PWMCLKEN_RAT_BITN 7
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#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080
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#define RFC_PWR_PWMCLKEN_RAT_S 7
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// Field: [6] RFERAM
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//
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// Enable clock to the RF Engine RAM module.
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#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040
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#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6
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#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040
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#define RFC_PWR_PWMCLKEN_RFERAM_S 6
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// Field: [5] RFE
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//
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// Enable clock to the RF Engine (RFE) module.
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#define RFC_PWR_PWMCLKEN_RFE 0x00000020
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#define RFC_PWR_PWMCLKEN_RFE_BITN 5
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#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020
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#define RFC_PWR_PWMCLKEN_RFE_S 5
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// Field: [4] MDMRAM
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//
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// Enable clock to the Modem RAM module.
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#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010
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#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4
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#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010
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#define RFC_PWR_PWMCLKEN_MDMRAM_S 4
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// Field: [3] MDM
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//
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// Enable clock to the Modem (MDM) module.
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#define RFC_PWR_PWMCLKEN_MDM 0x00000008
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#define RFC_PWR_PWMCLKEN_MDM_BITN 3
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#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008
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#define RFC_PWR_PWMCLKEN_MDM_S 3
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// Field: [2] CPERAM
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//
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// Enable clock to the Command and Packet Engine (CPE) RAM module. As part of
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// RF Core initialization, set this bit together with CPE bit to enable CPE to
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// boot.
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#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004
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#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2
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#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004
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#define RFC_PWR_PWMCLKEN_CPERAM_S 2
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// Field: [1] CPE
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//
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// Enable processor clock (hclk) to the Command and Packet Engine (CPE). As
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// part of RF Core initialization, set this bit together with CPERAM bit to
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// enable CPE to boot.
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#define RFC_PWR_PWMCLKEN_CPE 0x00000002
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#define RFC_PWR_PWMCLKEN_CPE_BITN 1
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#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002
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#define RFC_PWR_PWMCLKEN_CPE_S 1
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// Field: [0] RFC
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//
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// Enable essential clocks for the RF Core interface. This includes the
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// interconnect, the radio doorbell DBELL command interface, the power
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// management (PWR) clock control module, and bus clock (sclk) for the CPE. To
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// remove possibility of locking yourself out from the RF Core, this bit can
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// not be cleared. If you need to disable all clocks to the RF Core, see the
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// PRCM:RFCCLKG.CLK_EN register.
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#define RFC_PWR_PWMCLKEN_RFC 0x00000001
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#define RFC_PWR_PWMCLKEN_RFC_BITN 0
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#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001
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#define RFC_PWR_PWMCLKEN_RFC_S 0
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#endif // __RFC_PWR__
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