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114 lines
6.1 KiB
C
114 lines
6.1 KiB
C
/******************************************************************************
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* Filename: hw_ints_h
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* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017)
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* Revision: 48904
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_INTS_H__
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#define __HW_INTS_H__
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//*****************************************************************************
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//
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// The following are defines for the interrupt assignments.
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//
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//*****************************************************************************
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#define INT_NMI_FAULT 2 // NMI Fault
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#define INT_HARD_FAULT 3 // Hard Fault
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#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage)
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// Fault
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#define INT_BUS_FAULT 5 // Bus Fault
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#define INT_USAGE_FAULT 6 // Usage Fault
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#define INT_SVCALL 11 // Supervisor Call (SVCall)
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#define INT_DEBUG 12 // Debug Monitor
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#define INT_PENDSV 14 // Pending Service Call (PendSV)
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#define INT_SYSTICK 15 // SysTick Interrupt from the
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// System Timer in NVIC.
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#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC
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#define INT_I2C_IRQ 17 // Interrupt event from I2C
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#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE
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// Generated events
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#define INT_AON_RTC_COMB 20 // Event from AON_RTC
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#define INT_UART0_COMB 21 // UART0 combined interrupt
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#define INT_AUX_SWEV0 22 // AUX software event 0
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#define INT_SSI0_COMB 23 // SSI0 combined interrupt
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#define INT_SSI1_COMB 24 // SSI1 combined interrupt
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#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE
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// Generated events
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#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt
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#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command
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// Acknowledgement Interrupt
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#define INT_I2S_IRQ 28 // Interrupt event from I2S
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#define INT_AUX_SWEV1 29 // AUX software event 1
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#define INT_WDT_IRQ 30 // Watchdog interrupt event
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#define INT_GPT0A 31 // GPT0A interrupt event
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#define INT_GPT0B 32 // GPT0B interrupt event
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#define INT_GPT1A 33 // GPT1A interrupt event
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#define INT_GPT1B 34 // GPT1B interrupt event
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#define INT_GPT2A 35 // GPT2A interrupt event
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#define INT_GPT2B 36 // GPT2B interrupt event
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#define INT_GPT3A 37 // GPT3A interrupt event
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#define INT_GPT3B 38 // GPT3B interrupt event
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#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt
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// event
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#define INT_DMA_DONE_COMB 40 // Combined DMA done
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#define INT_DMA_ERR 41 // DMA bus error
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#define INT_FLASH 42 // FLASH controller error event
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#define INT_SWEV0 43 // Software event 0
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#define INT_AUX_COMB 44 // AUX combined event
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#define INT_AON_PROG0 45 // AON programmable event 0
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#define INT_PROG0 46 // Programmable Interrupt 0
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#define INT_AUX_COMPA 47 // AUX Compare A event
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#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event
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#define INT_TRNG_IRQ 49 // TRNG Interrupt event
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//*****************************************************************************
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//
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// The following are defines for number of interrupts and priority levels.
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//
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//*****************************************************************************
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#define NUM_INTERRUPTS 50 // Number of interrupts
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#define NUM_PRIORITY_BITS 3 // Number of Priority bits
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#define NUM_PRIORITY 8 // Number of priority levels
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//*****************************************************************************
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//
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// Aliases for backwards compatibility with Sensor Controller Studio 1.1.0
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//
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//*****************************************************************************
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#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0
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#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1
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#endif
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