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348 lines
15 KiB
C
348 lines
15 KiB
C
/******************************************************************************
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* Filename: hw_cpu_tpiu_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_CPU_TPIU_H__
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#define __HW_CPU_TPIU_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// CPU_TPIU component
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//
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//*****************************************************************************
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// Supported Sync Port Sizes
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#define CPU_TPIU_O_SSPSR 0x00000000
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// Current Sync Port Size
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#define CPU_TPIU_O_CSPSR 0x00000004
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// Async Clock Prescaler
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#define CPU_TPIU_O_ACPR 0x00000010
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// Selected Pin Protocol
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#define CPU_TPIU_O_SPPR 0x000000F0
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// Formatter and Flush Status
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#define CPU_TPIU_O_FFSR 0x00000300
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// Formatter and Flush Control
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#define CPU_TPIU_O_FFCR 0x00000304
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// Formatter Synchronization Counter
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#define CPU_TPIU_O_FSCR 0x00000308
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// Claim Tag Mask
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#define CPU_TPIU_O_CLAIMMASK 0x00000FA0
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// Claim Tag Set
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#define CPU_TPIU_O_CLAIMSET 0x00000FA0
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// Current Claim Tag
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#define CPU_TPIU_O_CLAIMTAG 0x00000FA4
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// Claim Tag Clear
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#define CPU_TPIU_O_CLAIMCLR 0x00000FA4
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// Device ID
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#define CPU_TPIU_O_DEVID 0x00000FC8
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_SSPSR
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//
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//*****************************************************************************
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// Field: [3] FOUR
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//
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// 4-bit port size support
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//
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// 0x0: Not supported
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// 0x1: Supported
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#define CPU_TPIU_SSPSR_FOUR 0x00000008
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#define CPU_TPIU_SSPSR_FOUR_BITN 3
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#define CPU_TPIU_SSPSR_FOUR_M 0x00000008
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#define CPU_TPIU_SSPSR_FOUR_S 3
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// Field: [2] THREE
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//
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// 3-bit port size support
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//
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// 0x0: Not supported
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// 0x1: Supported
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#define CPU_TPIU_SSPSR_THREE 0x00000004
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#define CPU_TPIU_SSPSR_THREE_BITN 2
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#define CPU_TPIU_SSPSR_THREE_M 0x00000004
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#define CPU_TPIU_SSPSR_THREE_S 2
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// Field: [1] TWO
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//
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// 2-bit port size support
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//
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// 0x0: Not supported
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// 0x1: Supported
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#define CPU_TPIU_SSPSR_TWO 0x00000002
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#define CPU_TPIU_SSPSR_TWO_BITN 1
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#define CPU_TPIU_SSPSR_TWO_M 0x00000002
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#define CPU_TPIU_SSPSR_TWO_S 1
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// Field: [0] ONE
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//
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// 1-bit port size support
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//
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// 0x0: Not supported
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// 0x1: Supported
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#define CPU_TPIU_SSPSR_ONE 0x00000001
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#define CPU_TPIU_SSPSR_ONE_BITN 0
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#define CPU_TPIU_SSPSR_ONE_M 0x00000001
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#define CPU_TPIU_SSPSR_ONE_S 0
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_CSPSR
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//
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//*****************************************************************************
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// Field: [3] FOUR
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//
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// 4-bit port enable
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// Writing values with more than one bit set in CSPSR, or setting a bit that is
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// not indicated as supported in SSPSR can cause Unpredictable behavior.
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#define CPU_TPIU_CSPSR_FOUR 0x00000008
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#define CPU_TPIU_CSPSR_FOUR_BITN 3
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#define CPU_TPIU_CSPSR_FOUR_M 0x00000008
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#define CPU_TPIU_CSPSR_FOUR_S 3
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// Field: [2] THREE
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//
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// 3-bit port enable
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// Writing values with more than one bit set in CSPSR, or setting a bit that is
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// not indicated as supported in SSPSR can cause Unpredictable behavior.
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#define CPU_TPIU_CSPSR_THREE 0x00000004
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#define CPU_TPIU_CSPSR_THREE_BITN 2
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#define CPU_TPIU_CSPSR_THREE_M 0x00000004
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#define CPU_TPIU_CSPSR_THREE_S 2
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// Field: [1] TWO
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//
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// 2-bit port enable
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// Writing values with more than one bit set in CSPSR, or setting a bit that is
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// not indicated as supported in SSPSR can cause Unpredictable behavior.
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#define CPU_TPIU_CSPSR_TWO 0x00000002
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#define CPU_TPIU_CSPSR_TWO_BITN 1
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#define CPU_TPIU_CSPSR_TWO_M 0x00000002
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#define CPU_TPIU_CSPSR_TWO_S 1
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// Field: [0] ONE
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//
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// 1-bit port enable
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// Writing values with more than one bit set in CSPSR, or setting a bit that is
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// not indicated as supported in SSPSR can cause Unpredictable behavior.
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#define CPU_TPIU_CSPSR_ONE 0x00000001
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#define CPU_TPIU_CSPSR_ONE_BITN 0
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#define CPU_TPIU_CSPSR_ONE_M 0x00000001
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#define CPU_TPIU_CSPSR_ONE_S 0
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_ACPR
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//
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//*****************************************************************************
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// Field: [12:0] PRESCALER
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//
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// Divisor for input trace clock is (PRESCALER + 1).
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#define CPU_TPIU_ACPR_PRESCALER_W 13
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#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF
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#define CPU_TPIU_ACPR_PRESCALER_S 0
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_SPPR
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//
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//*****************************************************************************
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// Field: [1:0] PROTOCOL
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//
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// Trace output protocol
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// ENUMs:
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// SWO_NRZ SerialWire Output (NRZ)
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// SWO_MANCHESTER SerialWire Output (Manchester). This is the reset
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// value.
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// TRACEPORT TracePort mode
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#define CPU_TPIU_SPPR_PROTOCOL_W 2
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#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003
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#define CPU_TPIU_SPPR_PROTOCOL_S 0
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#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002
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#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001
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#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_FFSR
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//
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//*****************************************************************************
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// Field: [3] FTNONSTOP
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//
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// 0: Formatter can be stopped
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// 1: Formatter cannot be stopped
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#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008
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#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3
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#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008
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#define CPU_TPIU_FFSR_FTNONSTOP_S 3
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_FFCR
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//
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//*****************************************************************************
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// Field: [8] TRIGIN
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//
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// Indicates that triggers are inserted when a trigger pin is asserted.
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#define CPU_TPIU_FFCR_TRIGIN 0x00000100
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#define CPU_TPIU_FFCR_TRIGIN_BITN 8
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#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100
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#define CPU_TPIU_FFCR_TRIGIN_S 8
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// Field: [1] ENFCONT
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//
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// Enable continuous formatting:
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//
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// 0: Continuous formatting disabled
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// 1: Continuous formatting enabled
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#define CPU_TPIU_FFCR_ENFCONT 0x00000002
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#define CPU_TPIU_FFCR_ENFCONT_BITN 1
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#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002
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#define CPU_TPIU_FFCR_ENFCONT_S 1
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_FSCR
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//
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//*****************************************************************************
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// Field: [31:0] FSCR
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//
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// The global synchronization trigger is generated by the Program Counter (PC)
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// Sampler block. This means that there is no synchronization counter in the
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// TPIU.
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#define CPU_TPIU_FSCR_FSCR_W 32
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#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF
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#define CPU_TPIU_FSCR_FSCR_S 0
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_CLAIMMASK
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//
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//*****************************************************************************
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// Field: [31:0] CLAIMMASK
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//
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// This register forms one half of the Claim Tag value. When reading this
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// register returns the number of bits that can be set (each bit is considered
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// separately):
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//
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// 0: This claim tag bit is not implemented
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// 1: This claim tag bit is not implemented
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//
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// The behavior when writing to this register is described in CLAIMSET.
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#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32
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#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF
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#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_CLAIMSET
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//
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//*****************************************************************************
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// Field: [31:0] CLAIMSET
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//
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// This register forms one half of the Claim Tag value. Writing to this
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// location allows individual bits to be set (each bit is considered
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// separately):
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//
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// 0: No effect
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// 1: Set this bit in the claim tag
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//
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// The behavior when reading from this location is described in CLAIMMASK.
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#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32
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#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF
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#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_CLAIMTAG
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//
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//*****************************************************************************
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// Field: [31:0] CLAIMTAG
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//
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// This register forms one half of the Claim Tag value. Reading this register
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// returns the current Claim Tag value.
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// Reading CLAIMMASK determines how many bits from this register must be used.
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//
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// The behavior when writing to this register is described in CLAIMCLR.
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#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32
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#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF
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#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_CLAIMCLR
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//
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//*****************************************************************************
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// Field: [31:0] CLAIMCLR
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//
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// This register forms one half of the Claim Tag value. Writing to this
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// location enables individual bits to be cleared (each bit is considered
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// separately):
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//
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// 0: No effect
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// 1: Clear this bit in the claim tag.
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//
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// The behavior when reading from this location is described in CLAIMTAG.
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#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32
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#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF
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#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0
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//*****************************************************************************
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//
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// Register: CPU_TPIU_O_DEVID
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//
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//*****************************************************************************
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// Field: [31:0] DEVID
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//
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// This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no
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// ETM present.
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#define CPU_TPIU_DEVID_DEVID_W 32
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#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF
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#define CPU_TPIU_DEVID_DEVID_S 0
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#endif // __CPU_TPIU__
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