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444 lines
19 KiB
C
444 lines
19 KiB
C
/******************************************************************************
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* Filename: hw_cpu_fpb_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_CPU_FPB_H__
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#define __HW_CPU_FPB_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// CPU_FPB component
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//
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//*****************************************************************************
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// Control
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#define CPU_FPB_O_CTRL 0x00000000
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// Remap
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#define CPU_FPB_O_REMAP 0x00000004
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// Comparator 0
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#define CPU_FPB_O_COMP0 0x00000008
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// Comparator 1
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#define CPU_FPB_O_COMP1 0x0000000C
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// Comparator 2
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#define CPU_FPB_O_COMP2 0x00000010
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// Comparator 3
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#define CPU_FPB_O_COMP3 0x00000014
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// Comparator 4
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#define CPU_FPB_O_COMP4 0x00000018
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// Comparator 5
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#define CPU_FPB_O_COMP5 0x0000001C
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// Comparator 6
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#define CPU_FPB_O_COMP6 0x00000020
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// Comparator 7
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#define CPU_FPB_O_COMP7 0x00000024
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//*****************************************************************************
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//
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// Register: CPU_FPB_O_CTRL
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//
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//*****************************************************************************
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// Field: [13:12] NUM_CODE2
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//
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// Number of full banks of code comparators, sixteen comparators per bank.
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// Where less than sixteen code comparators are provided, the bank count is
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// zero, and the number present indicated by NUM_CODE1. This read only field
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// contains 3'b000 to indicate 0 banks for Cortex-M processor.
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#define CPU_FPB_CTRL_NUM_CODE2_W 2
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#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000
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#define CPU_FPB_CTRL_NUM_CODE2_S 12
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// Field: [11:8] NUM_LIT
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//
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// Number of literal slots field.
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//
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// 0x0: No literal slots
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// 0x2: Two literal slots
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#define CPU_FPB_CTRL_NUM_LIT_W 4
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#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00
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#define CPU_FPB_CTRL_NUM_LIT_S 8
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// Field: [7:4] NUM_CODE1
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//
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// Number of code slots field.
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//
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// 0x0: No code slots
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// 0x2: Two code slots
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// 0x6: Six code slots
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#define CPU_FPB_CTRL_NUM_CODE1_W 4
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#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0
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#define CPU_FPB_CTRL_NUM_CODE1_S 4
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// Field: [1] KEY
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//
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// Key field. In order to write to this register, this bit-field must be
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// written to '1'. This bit always reads 0.
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#define CPU_FPB_CTRL_KEY 0x00000002
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#define CPU_FPB_CTRL_KEY_BITN 1
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#define CPU_FPB_CTRL_KEY_M 0x00000002
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#define CPU_FPB_CTRL_KEY_S 1
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// Field: [0] ENABLE
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//
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// Flash patch unit enable bit
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//
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// 0x0: Flash patch unit disabled
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// 0x1: Flash patch unit enabled
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#define CPU_FPB_CTRL_ENABLE 0x00000001
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#define CPU_FPB_CTRL_ENABLE_BITN 0
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#define CPU_FPB_CTRL_ENABLE_M 0x00000001
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#define CPU_FPB_CTRL_ENABLE_S 0
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//*****************************************************************************
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//
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// Register: CPU_FPB_O_REMAP
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//
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//*****************************************************************************
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// Field: [28:5] REMAP
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//
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// Remap base address field.
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#define CPU_FPB_REMAP_REMAP_W 24
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#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0
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#define CPU_FPB_REMAP_REMAP_S 5
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//*****************************************************************************
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//
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// Register: CPU_FPB_O_COMP0
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//
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//*****************************************************************************
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// Field: [31:30] REPLACE
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//
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// This selects what happens when the COMP address is matched. Address
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// remapping only takes place for the 0x0 setting.
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//
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// 0x0: Remap to remap address. See REMAP.REMAP
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// 0x1: Set BKPT on lower halfword, upper is unaffected
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// 0x2: Set BKPT on upper halfword, lower is unaffected
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// 0x3: Set BKPT on both lower and upper halfwords.
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#define CPU_FPB_COMP0_REPLACE_W 2
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#define CPU_FPB_COMP0_REPLACE_M 0xC0000000
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#define CPU_FPB_COMP0_REPLACE_S 30
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// Field: [28:2] COMP
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//
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// Comparison address.
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#define CPU_FPB_COMP0_COMP_W 27
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#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC
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#define CPU_FPB_COMP0_COMP_S 2
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// Field: [0] ENABLE
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//
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// Compare and remap enable comparator 0. CTRL.ENABLE must also be set to
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// enable comparisons.
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//
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// 0x0: Compare and remap for comparator 0 disabled
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// 0x1: Compare and remap for comparator 0 enabled
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#define CPU_FPB_COMP0_ENABLE 0x00000001
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#define CPU_FPB_COMP0_ENABLE_BITN 0
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#define CPU_FPB_COMP0_ENABLE_M 0x00000001
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#define CPU_FPB_COMP0_ENABLE_S 0
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//*****************************************************************************
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//
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// Register: CPU_FPB_O_COMP1
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//
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//*****************************************************************************
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// Field: [31:30] REPLACE
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//
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// This selects what happens when the COMP address is matched. Address
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// remapping only takes place for the 0x0 setting.
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//
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// 0x0: Remap to remap address. See REMAP.REMAP
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// 0x1: Set BKPT on lower halfword, upper is unaffected
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// 0x2: Set BKPT on upper halfword, lower is unaffected
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// 0x3: Set BKPT on both lower and upper halfwords.
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#define CPU_FPB_COMP1_REPLACE_W 2
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#define CPU_FPB_COMP1_REPLACE_M 0xC0000000
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#define CPU_FPB_COMP1_REPLACE_S 30
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// Field: [28:2] COMP
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//
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// Comparison address.
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#define CPU_FPB_COMP1_COMP_W 27
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#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC
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#define CPU_FPB_COMP1_COMP_S 2
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// Field: [0] ENABLE
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//
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// Compare and remap enable comparator 1. CTRL.ENABLE must also be set to
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// enable comparisons.
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//
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// 0x0: Compare and remap for comparator 1 disabled
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// 0x1: Compare and remap for comparator 1 enabled
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#define CPU_FPB_COMP1_ENABLE 0x00000001
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#define CPU_FPB_COMP1_ENABLE_BITN 0
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#define CPU_FPB_COMP1_ENABLE_M 0x00000001
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#define CPU_FPB_COMP1_ENABLE_S 0
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//*****************************************************************************
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//
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// Register: CPU_FPB_O_COMP2
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//
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//*****************************************************************************
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// Field: [31:30] REPLACE
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//
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// This selects what happens when the COMP address is matched. Address
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// remapping only takes place for the 0x0 setting.
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//
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// 0x0: Remap to remap address. See REMAP.REMAP
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// 0x1: Set BKPT on lower halfword, upper is unaffected
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// 0x2: Set BKPT on upper halfword, lower is unaffected
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// 0x3: Set BKPT on both lower and upper halfwords.
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#define CPU_FPB_COMP2_REPLACE_W 2
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#define CPU_FPB_COMP2_REPLACE_M 0xC0000000
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#define CPU_FPB_COMP2_REPLACE_S 30
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// Field: [28:2] COMP
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//
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// Comparison address.
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#define CPU_FPB_COMP2_COMP_W 27
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#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC
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#define CPU_FPB_COMP2_COMP_S 2
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// Field: [0] ENABLE
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//
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// Compare and remap enable comparator 2. CTRL.ENABLE must also be set to
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// enable comparisons.
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//
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// 0x0: Compare and remap for comparator 2 disabled
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// 0x1: Compare and remap for comparator 2 enabled
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#define CPU_FPB_COMP2_ENABLE 0x00000001
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#define CPU_FPB_COMP2_ENABLE_BITN 0
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#define CPU_FPB_COMP2_ENABLE_M 0x00000001
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#define CPU_FPB_COMP2_ENABLE_S 0
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//*****************************************************************************
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//
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// Register: CPU_FPB_O_COMP3
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//
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//*****************************************************************************
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// Field: [31:30] REPLACE
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//
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// This selects what happens when the COMP address is matched. Address
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// remapping only takes place for the 0x0 setting.
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//
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// 0x0: Remap to remap address. See REMAP.REMAP
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// 0x1: Set BKPT on lower halfword, upper is unaffected
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// 0x2: Set BKPT on upper halfword, lower is unaffected
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// 0x3: Set BKPT on both lower and upper halfwords.
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#define CPU_FPB_COMP3_REPLACE_W 2
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#define CPU_FPB_COMP3_REPLACE_M 0xC0000000
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#define CPU_FPB_COMP3_REPLACE_S 30
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// Field: [28:2] COMP
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//
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// Comparison address.
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#define CPU_FPB_COMP3_COMP_W 27
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#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC
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#define CPU_FPB_COMP3_COMP_S 2
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// Field: [0] ENABLE
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//
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// Compare and remap enable comparator 3. CTRL.ENABLE must also be set to
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// enable comparisons.
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//
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// 0x0: Compare and remap for comparator 3 disabled
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// 0x1: Compare and remap for comparator 3 enabled
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#define CPU_FPB_COMP3_ENABLE 0x00000001
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#define CPU_FPB_COMP3_ENABLE_BITN 0
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#define CPU_FPB_COMP3_ENABLE_M 0x00000001
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#define CPU_FPB_COMP3_ENABLE_S 0
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//*****************************************************************************
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//
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// Register: CPU_FPB_O_COMP4
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//
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//*****************************************************************************
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// Field: [31:30] REPLACE
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//
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// This selects what happens when the COMP address is matched. Address
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// remapping only takes place for the 0x0 setting.
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//
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// 0x0: Remap to remap address. See REMAP.REMAP
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// 0x1: Set BKPT on lower halfword, upper is unaffected
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// 0x2: Set BKPT on upper halfword, lower is unaffected
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// 0x3: Set BKPT on both lower and upper halfwords.
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#define CPU_FPB_COMP4_REPLACE_W 2
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#define CPU_FPB_COMP4_REPLACE_M 0xC0000000
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#define CPU_FPB_COMP4_REPLACE_S 30
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// Field: [28:2] COMP
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//
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// Comparison address.
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#define CPU_FPB_COMP4_COMP_W 27
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#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC
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#define CPU_FPB_COMP4_COMP_S 2
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// Field: [0] ENABLE
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//
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// Compare and remap enable comparator 4. CTRL.ENABLE must also be set to
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// enable comparisons.
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//
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// 0x0: Compare and remap for comparator 4 disabled
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// 0x1: Compare and remap for comparator 4 enabled
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#define CPU_FPB_COMP4_ENABLE 0x00000001
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#define CPU_FPB_COMP4_ENABLE_BITN 0
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#define CPU_FPB_COMP4_ENABLE_M 0x00000001
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#define CPU_FPB_COMP4_ENABLE_S 0
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//*****************************************************************************
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//
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// Register: CPU_FPB_O_COMP5
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//
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//*****************************************************************************
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// Field: [31:30] REPLACE
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//
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// This selects what happens when the COMP address is matched. Address
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// remapping only takes place for the 0x0 setting.
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//
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// 0x0: Remap to remap address. See REMAP.REMAP
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// 0x1: Set BKPT on lower halfword, upper is unaffected
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// 0x2: Set BKPT on upper halfword, lower is unaffected
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// 0x3: Set BKPT on both lower and upper halfwords.
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#define CPU_FPB_COMP5_REPLACE_W 2
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#define CPU_FPB_COMP5_REPLACE_M 0xC0000000
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#define CPU_FPB_COMP5_REPLACE_S 30
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// Field: [28:2] COMP
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//
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// Comparison address.
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#define CPU_FPB_COMP5_COMP_W 27
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#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC
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#define CPU_FPB_COMP5_COMP_S 2
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// Field: [0] ENABLE
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//
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// Compare and remap enable comparator 5. CTRL.ENABLE must also be set to
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// enable comparisons.
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//
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// 0x0: Compare and remap for comparator 5 disabled
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// 0x1: Compare and remap for comparator 5 enabled
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#define CPU_FPB_COMP5_ENABLE 0x00000001
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#define CPU_FPB_COMP5_ENABLE_BITN 0
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#define CPU_FPB_COMP5_ENABLE_M 0x00000001
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#define CPU_FPB_COMP5_ENABLE_S 0
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//*****************************************************************************
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//
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// Register: CPU_FPB_O_COMP6
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//
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//*****************************************************************************
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// Field: [31:30] REPLACE
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//
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// This selects what happens when the COMP address is matched. Comparator 6 is
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// a literal comparator and the only supported setting is 0x0. Other settings
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// will be ignored.
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//
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// 0x0: Remap to remap address. See REMAP.REMAP
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// 0x1: Set BKPT on lower halfword, upper is unaffected
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// 0x2: Set BKPT on upper halfword, lower is unaffected
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// 0x3: Set BKPT on both lower and upper halfwords.
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#define CPU_FPB_COMP6_REPLACE_W 2
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#define CPU_FPB_COMP6_REPLACE_M 0xC0000000
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#define CPU_FPB_COMP6_REPLACE_S 30
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// Field: [28:2] COMP
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//
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// Comparison address.
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#define CPU_FPB_COMP6_COMP_W 27
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#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC
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#define CPU_FPB_COMP6_COMP_S 2
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// Field: [0] ENABLE
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//
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// Compare and remap enable comparator 6. CTRL.ENABLE must also be set to
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// enable comparisons.
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//
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// 0x0: Compare and remap for comparator 6 disabled
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// 0x1: Compare and remap for comparator 6 enabled
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#define CPU_FPB_COMP6_ENABLE 0x00000001
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#define CPU_FPB_COMP6_ENABLE_BITN 0
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#define CPU_FPB_COMP6_ENABLE_M 0x00000001
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#define CPU_FPB_COMP6_ENABLE_S 0
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//*****************************************************************************
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//
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// Register: CPU_FPB_O_COMP7
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//
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//*****************************************************************************
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// Field: [31:30] REPLACE
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//
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// This selects what happens when the COMP address is matched. Comparator 7 is
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// a literal comparator and the only supported setting is 0x0. Other settings
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// will be ignored.
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//
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// 0x0: Remap to remap address. See REMAP.REMAP
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// 0x1: Set BKPT on lower halfword, upper is unaffected
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// 0x2: Set BKPT on upper halfword, lower is unaffected
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// 0x3: Set BKPT on both lower and upper halfwords.
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#define CPU_FPB_COMP7_REPLACE_W 2
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#define CPU_FPB_COMP7_REPLACE_M 0xC0000000
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#define CPU_FPB_COMP7_REPLACE_S 30
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// Field: [28:2] COMP
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//
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// Comparison address.
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#define CPU_FPB_COMP7_COMP_W 27
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#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC
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#define CPU_FPB_COMP7_COMP_S 2
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// Field: [0] ENABLE
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//
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// Compare and remap enable comparator 7. CTRL.ENABLE must also be set to
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// enable comparisons.
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//
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// 0x0: Compare and remap for comparator 7 disabled
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// 0x1: Compare and remap for comparator 7 enabled
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#define CPU_FPB_COMP7_ENABLE 0x00000001
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#define CPU_FPB_COMP7_ENABLE_BITN 0
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#define CPU_FPB_COMP7_ENABLE_M 0x00000001
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#define CPU_FPB_COMP7_ENABLE_S 0
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#endif // __CPU_FPB__
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