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482 lines
21 KiB
C
482 lines
21 KiB
C
/******************************************************************************
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* Filename: hw_aux_aiodio_h
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* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017)
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* Revision: 49005
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_AUX_AIODIO_H__
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#define __HW_AUX_AIODIO_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// AUX_AIODIO component
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//
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//*****************************************************************************
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// General Purpose Input Output Data Out
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#define AUX_AIODIO_O_GPIODOUT 0x00000000
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// Input Output Mode
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#define AUX_AIODIO_O_IOMODE 0x00000004
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// General Purpose Input Output Data In
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#define AUX_AIODIO_O_GPIODIN 0x00000008
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// General Purpose Input Output Data Out Set
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#define AUX_AIODIO_O_GPIODOUTSET 0x0000000C
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// General Purpose Input Output Data Out Clear
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#define AUX_AIODIO_O_GPIODOUTCLR 0x00000010
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// General Purpose Input Output Data Out Toggle
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#define AUX_AIODIO_O_GPIODOUTTGL 0x00000014
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// General Purpose Input Output Digital Input Enable
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#define AUX_AIODIO_O_GPIODIE 0x00000018
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//*****************************************************************************
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//
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// Register: AUX_AIODIO_O_GPIODOUT
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//
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//*****************************************************************************
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// Field: [7:0] IO7_0
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//
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// Write 1 to bit index n in this bit vector to set AUXIO[8i+n].
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// Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].
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#define AUX_AIODIO_GPIODOUT_IO7_0_W 8
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#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF
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#define AUX_AIODIO_GPIODOUT_IO7_0_S 0
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//*****************************************************************************
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//
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// Register: AUX_AIODIO_O_IOMODE
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//
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//*****************************************************************************
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// Field: [15:14] IO7
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//
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// Select mode for AUXIO[8i+7].
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// ENUMs:
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// OPEN_SOURCE Open-Source Mode:
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//
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// When GPIODOUT bit 7 is 0:
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// AUXIO[8i+7] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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//
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// When GPIODOUT bit 7 is 1:
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// AUXIO[8i+7] is driven high.
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// OPEN_DRAIN Open-Drain Mode:
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//
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// When GPIODOUT bit 7 is 0:
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// AUXIO[8i+7] is driven low.
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//
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// When GPIODOUT bit 7 is 1:
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// AUXIO[8i+7] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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// IN Input Mode:
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//
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// When GPIODIE bit 7 is 0:
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// AUXIO[8i+7] is enabled for analog signal
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// transfer.
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//
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// When GPIODIE bit 7 is 1:
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// AUXIO[8i+7] is enabled for digital input.
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// OUT Output Mode:
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//
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// GPIODOUT bit 7 drives
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// AUXIO[8i+7].
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#define AUX_AIODIO_IOMODE_IO7_W 2
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#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000
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#define AUX_AIODIO_IOMODE_IO7_S 14
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#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000
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#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000
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#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000
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#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000
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// Field: [13:12] IO6
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//
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// Select mode for AUXIO[8i+6].
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// ENUMs:
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// OPEN_SOURCE Open-Source Mode:
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//
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// When GPIODOUT bit 6 is 0:
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// AUXIO[8i+6] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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//
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// When GPIODOUT bit 6 is 1:
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// AUXIO[8i+6] is driven high.
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// OPEN_DRAIN Open-Drain Mode:
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//
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// When GPIODOUT bit 6 is 0:
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// AUXIO[8i+6] is driven low.
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//
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// When GPIODOUT bit 6 is 1:
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// AUXIO[8i+6] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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// IN Input Mode:
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//
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// When GPIODIE bit 6 is 0:
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// AUXIO[8i+6] is enabled for analog signal
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// transfer.
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//
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// When GPIODIE bit 6 is 1:
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// AUXIO[8i+6] is enabled for digital input.
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// OUT Output Mode:
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//
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// GPIODOUT bit 6 drives
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// AUXIO[8i+6].
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#define AUX_AIODIO_IOMODE_IO6_W 2
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#define AUX_AIODIO_IOMODE_IO6_M 0x00003000
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#define AUX_AIODIO_IOMODE_IO6_S 12
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#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000
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#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000
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#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000
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#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000
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// Field: [11:10] IO5
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//
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// Select mode for AUXIO[8i+5].
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// ENUMs:
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// OPEN_SOURCE Open-Source Mode:
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//
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// When GPIODOUT bit 5 is 0:
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// AUXIO[8i+5] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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//
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// When GPIODOUT bit 5 is 1:
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// AUXIO[8i+5] is driven high.
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// OPEN_DRAIN Open-Drain Mode:
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//
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// When GPIODOUT bit 5 is 0:
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// AUXIO[8i+5] is driven low.
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//
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// When GPIODOUT bit 5 is 1:
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// AUXIO[8i+5] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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// IN Input Mode:
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//
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// When GPIODIE bit 5 is 0:
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// AUXIO[8i+5] is enabled for analog signal
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// transfer.
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//
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// When GPIODIE bit 5 is 1:
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// AUXIO[8i+5] is enabled for digital input.
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// OUT Output Mode:
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//
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// GPIODOUT bit 5 drives
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// AUXIO[8i+5].
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#define AUX_AIODIO_IOMODE_IO5_W 2
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#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00
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#define AUX_AIODIO_IOMODE_IO5_S 10
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#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00
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#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800
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#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400
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#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000
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// Field: [9:8] IO4
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//
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// Select mode for AUXIO[8i+4].
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// ENUMs:
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// OPEN_SOURCE Open-Source Mode:
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//
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// When GPIODOUT bit 4 is 0:
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// AUXIO[8i+4] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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//
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// When GPIODOUT bit 4 is 1:
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// AUXIO[8i+4] is driven high.
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// OPEN_DRAIN Open-Drain Mode:
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//
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// When GPIODOUT bit 4 is 0:
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// AUXIO[8i+4] is driven low.
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//
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// When GPIODOUT bit 4 is 1:
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// AUXIO[8i+4] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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// IN Input Mode:
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//
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// When GPIODIE bit 4 is 0:
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// AUXIO[8i+4] is enabled for analog signal
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// transfer.
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//
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// When GPIODIE bit 4 is 1:
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// AUXIO[8i+4] is enabled for digital input.
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// OUT Output Mode:
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//
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// GPIODOUT bit 4 drives
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// AUXIO[8i+4].
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#define AUX_AIODIO_IOMODE_IO4_W 2
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#define AUX_AIODIO_IOMODE_IO4_M 0x00000300
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#define AUX_AIODIO_IOMODE_IO4_S 8
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#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300
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#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200
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#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100
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#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000
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// Field: [7:6] IO3
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//
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// Select mode for AUXIO[8i+3].
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// ENUMs:
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// OPEN_SOURCE Open-Source Mode:
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//
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// When GPIODOUT bit 3 is 0:
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// AUXIO[8i+3] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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//
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// When GPIODOUT bit 3 is 1:
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// AUXIO[8i+3] is driven high.
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// OPEN_DRAIN Open-Drain Mode:
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//
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// When GPIODOUT bit 3 is 0:
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// AUXIO[8i+3] is driven low.
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//
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// When GPIODOUT bit 3 is 1:
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// AUXIO[8i+3] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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// IN Input Mode:
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//
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// When GPIODIE bit 3 is 0:
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// AUXIO[8i+3] is enabled for analog signal
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// transfer.
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//
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// When GPIODIE bit 3 is 1:
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// AUXIO[8i+3] is enabled for digital input.
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// OUT Output Mode:
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//
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// GPIODOUT bit 3 drives
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// AUXIO[8i+3].
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#define AUX_AIODIO_IOMODE_IO3_W 2
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#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0
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#define AUX_AIODIO_IOMODE_IO3_S 6
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#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0
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#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080
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#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040
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#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000
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// Field: [5:4] IO2
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//
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// Select mode for AUXIO[8i+2].
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// ENUMs:
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// OPEN_SOURCE Open-Source Mode:
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//
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// When GPIODOUT bit 2 is 0:
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// AUXIO[8i+2] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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//
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// When GPIODOUT bit 2 is 1:
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// AUXIO[8i+2] is driven high.
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// OPEN_DRAIN Open-Drain Mode:
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//
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// When GPIODOUT bit 2 is 0:
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// AUXIO[8i+2] is driven low.
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//
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// When GPIODOUT bit 2 is 1:
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// AUXIO[8i+2] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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// IN Input Mode:
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//
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// When GPIODIE bit 2 is 0:
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// AUXIO[8i+2] is enabled for analog signal
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// transfer.
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//
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// When GPIODIE bit 2 is 1:
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// AUXIO[8i+2] is enabled for digital input.
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// OUT Output Mode:
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//
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// GPIODOUT bit 2 drives
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// AUXIO[8i+2].
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#define AUX_AIODIO_IOMODE_IO2_W 2
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#define AUX_AIODIO_IOMODE_IO2_M 0x00000030
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#define AUX_AIODIO_IOMODE_IO2_S 4
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#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030
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#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020
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#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010
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#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000
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// Field: [3:2] IO1
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//
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// Select mode for AUXIO[8i+1].
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// ENUMs:
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// OPEN_SOURCE Open-Source Mode:
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//
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// When GPIODOUT bit 1 is 0:
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// AUXIO[8i+1] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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//
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// When GPIODOUT bit 1 is 1:
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// AUXIO[8i+1] is driven high.
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// OPEN_DRAIN Open-Drain Mode:
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//
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// When GPIODOUT bit 1 is 0:
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// AUXIO[8i+1] is driven low.
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//
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// When GPIODOUT bit 1 is 1:
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// AUXIO[8i+1] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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// IN Input Mode:
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//
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// When GPIODIE bit 1 is 0:
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// AUXIO[8i+1] is enabled for analog signal
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// transfer.
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//
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// When GPIODIE bit 1 is 1:
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// AUXIO[8i+1] is enabled for digital input.
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// OUT Output Mode:
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//
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// GPIODOUT bit 1 drives
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// AUXIO[8i+1].
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#define AUX_AIODIO_IOMODE_IO1_W 2
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#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C
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#define AUX_AIODIO_IOMODE_IO1_S 2
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#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C
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#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008
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#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004
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#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000
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// Field: [1:0] IO0
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//
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// Select mode for AUXIO[8i+0].
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// ENUMs:
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// OPEN_SOURCE Open-Source Mode:
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//
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// When GPIODOUT bit 0 is 0:
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// AUXIO[8i+0] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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//
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// When GPIODOUT bit 0 is 1:
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// AUXIO[8i+0] is driven high.
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// OPEN_DRAIN Open-Drain Mode:
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//
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// When GPIODOUT bit 0 is 0:
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// AUXIO[8i+0] is driven low.
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//
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// When GPIODOUT bit 0 is 1:
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// AUXIO[8i+0] is tri-stated or pulled. This
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// depends on IOC:IOCFGn.PULL_CTL.
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// IN Input Mode:
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//
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// When GPIODIE bit 0 is 0:
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// AUXIO[8i+0] is enabled for analog signal
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// transfer.
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//
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// When GPIODIE bit 0 is 1:
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// AUXIO[8i+0] is enabled for digital input.
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// OUT Output Mode:
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//
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// GPIODOUT bit 0 drives
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// AUXIO[8i+0].
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#define AUX_AIODIO_IOMODE_IO0_W 2
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#define AUX_AIODIO_IOMODE_IO0_M 0x00000003
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#define AUX_AIODIO_IOMODE_IO0_S 0
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#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003
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#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002
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#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001
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#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000
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//*****************************************************************************
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//
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// Register: AUX_AIODIO_O_GPIODIN
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//
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//*****************************************************************************
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// Field: [7:0] IO7_0
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//
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// Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit
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// n is set. Otherwise, bit n value is old.
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#define AUX_AIODIO_GPIODIN_IO7_0_W 8
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#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF
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#define AUX_AIODIO_GPIODIN_IO7_0_S 0
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//*****************************************************************************
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//
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// Register: AUX_AIODIO_O_GPIODOUTSET
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//
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//*****************************************************************************
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// Field: [7:0] IO7_0
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//
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// Write 1 to bit index n in this bit vector to set GPIODOUT bit n.
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//
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// Read value is 0.
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#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8
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#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF
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#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0
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//*****************************************************************************
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//
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// Register: AUX_AIODIO_O_GPIODOUTCLR
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//
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//*****************************************************************************
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// Field: [7:0] IO7_0
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//
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// Write 1 to bit index n in this bit vector to clear GPIODOUT bit n.
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//
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// Read value is 0.
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#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8
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#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF
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#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0
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//*****************************************************************************
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//
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// Register: AUX_AIODIO_O_GPIODOUTTGL
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//
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//*****************************************************************************
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// Field: [7:0] IO7_0
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//
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// Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n.
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//
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// Read value is 0.
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#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8
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#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF
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#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0
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//*****************************************************************************
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//
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// Register: AUX_AIODIO_O_GPIODIE
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//
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//*****************************************************************************
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// Field: [7:0] IO7_0
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//
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// Write 1 to bit index n in this bit vector to enable digital input buffer for
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// AUXIO[8i+n].
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// Write 0 to bit index n in this bit vector to disable digital input buffer
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// for AUXIO[8i+n].
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//
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// You must enable the digital input buffer for AUXIO[8i+n] to read the pin
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// value in GPIODIN.
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// You must disable the digital input buffer for analog input or pins that
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// float to avoid current leakage.
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#define AUX_AIODIO_GPIODIE_IO7_0_W 8
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#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF
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#define AUX_AIODIO_GPIODIE_IO7_0_S 0
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#endif // __AUX_AIODIO__
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