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357 lines
16 KiB
C
357 lines
16 KiB
C
/******************************************************************************
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* Filename: setup.c
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* Revised: 2018-11-06 15:08:57 +0100 (Tue, 06 Nov 2018)
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* Revision: 53239
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*
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* Description: Setup file for CC13xx/CC26xx devices.
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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// Hardware headers
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#include "../inc/hw_types.h"
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#include "../inc/hw_memmap.h"
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#include "../inc/hw_adi.h"
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#include "../inc/hw_adi_2_refsys.h"
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#include "../inc/hw_adi_3_refsys.h"
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#include "../inc/hw_aon_ioc.h"
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#include "../inc/hw_aon_sysctl.h"
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#include "../inc/hw_aon_wuc.h"
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#include "../inc/hw_aux_wuc.h"
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#include "../inc/hw_ccfg.h"
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#include "../inc/hw_fcfg1.h"
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#include "../inc/hw_flash.h"
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#include "../inc/hw_prcm.h"
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#include "../inc/hw_vims.h"
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// Driverlib headers
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#include "aon_wuc.h"
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#include "aux_wuc.h"
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#include "chipinfo.h"
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#include "setup.h"
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#include "setup_rom.h"
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#include "cpu.h"
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//*****************************************************************************
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//
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// Handle support for DriverLib in ROM:
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// This section will undo prototype renaming made in the header file
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//
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//*****************************************************************************
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#if !defined(DOXYGEN)
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#undef SetupTrimDevice
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#define SetupTrimDevice NOROM_SetupTrimDevice
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#endif
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//*****************************************************************************
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//
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// Defined CPU delay macro with microseconds as input
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// Quick check shows: (To be further investigated)
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// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 5 cycles
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// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 1, there is 4 cycles
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// At 24 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 3 cycles
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//
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//*****************************************************************************
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#define CPU_DELAY_MICRO_SECONDS( x ) \
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CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 )
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//*****************************************************************************
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//
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// Function declarations
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//
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//*****************************************************************************
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static void TrimAfterColdReset( void );
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static void TrimAfterColdResetWakeupFromShutDown( uint32_t ui32Fcfg1Revision );
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static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void );
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//*****************************************************************************
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//
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// Perform the necessary trim of the device which is not done in boot code
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//
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// This function should only execute coming from ROM boot. The current
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// implementation does not take soft reset into account. However, it does no
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// damage to execute it again. It only consumes time.
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//
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//*****************************************************************************
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void
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SetupTrimDevice(void)
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{
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uint32_t ui32Fcfg1Revision;
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uint32_t ui32AonSysResetctl;
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// Get layout revision of the factory configuration area
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// (Handle undefined revision as revision = 0)
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ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION);
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if ( ui32Fcfg1Revision == 0xFFFFFFFF ) {
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ui32Fcfg1Revision = 0;
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}
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// This driverlib version and setup file is for CC26x0 PG2.2 and later
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// Halt if violated
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ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated();
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// Enable standby in flash bank
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HWREGBITW( FLASH_BASEADDR + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
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// Clock must always be enabled for the semaphore module (due to ADI/DDI HW workaround)
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HWREG( AUX_WUC_BASE + AUX_WUC_O_MODCLKEN1 ) = AUX_WUC_MODCLKEN1_SMPH;
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// Warm resets on CC13x0 and CC26x0 complicates software design because much of
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// our software expect that initialization is done from a full system reset.
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// This includes RTC setup, oscillator configuration and AUX setup.
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// To ensure a full reset of the device is done when customers get e.g. a Watchdog
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// reset, the following is set here:
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HWREGBITW( PRCM_BASE + PRCM_O_WARMRESET, PRCM_WARMRESET_WR_TO_PINRESET_BITN ) = 1;
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// Select correct CACHE mode and set correct CACHE configuration
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#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
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SetupSetCacheModeAccordingToCcfgSetting();
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#else
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NOROM_SetupSetCacheModeAccordingToCcfgSetting();
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#endif
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// 1. Check for powerdown
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// 2. Check for shutdown
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// 3. Assume cold reset if none of the above.
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//
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// It is always assumed that the application will freeze the latches in
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// AON_IOC when going to powerdown in order to retain the values on the IOs.
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//
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// NB. If this bit is not cleared before proceeding to powerdown, the IOs
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// will all default to the reset configuration when restarting.
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if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN )))
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{
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// NB. This should be calling a ROM implementation of required trim and
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// compensation
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// e.g. TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()
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TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
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}
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// Check for shutdown
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//
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// When device is going to shutdown the hardware will automatically clear
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// the SLEEPDIS bit in the SLEEP register in the AON_SYSCTL module.
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// It is left for the application to assert this bit when waking back up,
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// but not before the desired IO configuration has been re-established.
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else if( ! ( HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL, AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN )))
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{
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// NB. This should be calling a ROM implementation of required trim and
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// compensation
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// e.g. TrimAfterColdResetWakeupFromShutDown() -->
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// TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
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TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision);
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TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
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}
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else
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{
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// Consider adding a check for soft reset to allow debugging to skip
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// this section!!!
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//
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// NB. This should be calling a ROM implementation of required trim and
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// compensation
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// e.g. TrimAfterColdReset() -->
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// TrimAfterColdResetWakeupFromShutDown() -->
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// TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()
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TrimAfterColdReset();
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TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision);
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TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
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}
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// Set VIMS power domain control.
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// PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered
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HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0;
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// Configure optimal wait time for flash FSM in cases where flash pump
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// wakes up from sleep
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HWREG(FLASH_BASEADDR + FLASH_O_FPAC1) = (HWREG(FLASH_BASEADDR + FLASH_O_FPAC1) &
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~FLASH_FPAC1_PSLEEPTDIS_M) |
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(0x139<<FLASH_FPAC1_PSLEEPTDIS_S);
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// And finally at the end of the flash boot process:
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// SET BOOT_DET bits in AON_SYSCTL to 3 if already found to be 1
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// Note: The BOOT_DET_x_CLR/SET bits must be manually cleared
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if ((( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) &
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( AON_SYSCTL_RESETCTL_BOOT_DET_1_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_M )) >>
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AON_SYSCTL_RESETCTL_BOOT_DET_0_S ) == 1 )
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{
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ui32AonSysResetctl = ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) &
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~( AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M |
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AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M ));
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HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M;
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HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl;
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}
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// Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice()
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// (There should typically be no wait time here, but need to be sure)
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while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) {
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// Do nothing - wait for an eventual ongoing mode change to complete.
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}
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}
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//*****************************************************************************
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//
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//! \brief Trims to be applied when coming from POWER_DOWN (also called when
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//! coming from SHUTDOWN and PIN_RESET).
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//!
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//! \return None
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//
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//*****************************************************************************
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static void
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TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void )
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{
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// Currently no specific trim for Powerdown
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}
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//*****************************************************************************
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//
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//! \brief Trims to be applied when coming from SHUTDOWN (also called when
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//! coming from PIN_RESET).
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//!
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//! \param ui32Fcfg1Revision
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//!
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//! \return None
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//
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//*****************************************************************************
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static void
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TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision)
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{
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uint32_t ccfg_ModeConfReg ;
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uint32_t mp1rev ;
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// Force AUX on and enable clocks
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//
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// No need to save the current status of the power/clock registers.
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// At this point both AUX and AON should have been reset to 0x0.
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HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) = AON_WUC_AUXCTL_AUX_FORCE_ON;
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// Wait for power on on the AUX domain
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while( ! ( HWREGBITW( AON_WUC_BASE + AON_WUC_O_PWRSTAT, AON_WUC_PWRSTAT_AUX_PD_ON_BITN )));
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// Enable the clocks for AUX_DDI0_OSC and AUX_ADI4
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HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) = AUX_WUC_MODCLKEN0_AUX_DDI0_OSC |
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AUX_WUC_MODCLKEN0_AUX_ADI4;
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// It's found to be optimal to override the FCFG1..DCDC_IPEAK setting as follows:
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// if ( alternative DCDC setting in CCFG is enabled ) ADI3..IPEAK = CCFG..DCDC_IPEAK
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// else ADI3..IPEAK = 2
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if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) {
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// ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=ALT_DCDC_DITHER_EN)
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// ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK )
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// Using a single 4-bit masked write since layout is equal for both source and destination
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HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 |
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( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ));
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} else {
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HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = 0x72;
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}
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//
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// Enable for JTAG to be powered down (will still be powered on if debugger is connected)
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AONWUCJtagPowerOff();
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// read the MODE_CONF register in CCFG
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ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
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// First part of trim done after cold reset and wakeup from shutdown:
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// -Adjust the VDDR_TRIM_SLEEP value.
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// -Configure DCDC.
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SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg );
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// Second part of trim done after cold reset and wakeup from shutdown:
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// -Configure XOSC.
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#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
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SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
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#else
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NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
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#endif
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// Increased margin between digital supply voltage and VDD BOD during standby.
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// VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7)
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// VTRIM_BOD: unsigned 4 bits value to be decremented by 1 (min = 0)
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// This applies to chips with mp1rev < 542 for cc13x0 and for mp1rev < 527 for cc26x0
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mp1rev = (( HWREG( FCFG1_BASE + FCFG1_O_TRIM_CAL_REVISION ) & FCFG1_TRIM_CAL_REVISION_MP1_M ) >>
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FCFG1_TRIM_CAL_REVISION_MP1_S ) ;
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if ( mp1rev < 527 ) {
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uint32_t ldoTrimReg = HWREG( FCFG1_BASE + FCFG1_O_BAT_RC_LDO_TRIM );
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uint32_t vtrim_bod = (( ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M ) >>
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FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S ); // bit[27:24] unsigned
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uint32_t vtrim_udig = (( ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M ) >>
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FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S ); // bit[19:16] signed but treated as unsigned
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if ( vtrim_bod > 0 ) {
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vtrim_bod -= 1;
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}
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if ( vtrim_udig != 7 ) {
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if ( vtrim_udig == 6 ) {
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vtrim_udig = 7;
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} else {
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vtrim_udig = (( vtrim_udig + 2 ) & 0xF );
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}
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}
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HWREGB( ADI2_BASE + ADI_2_REFSYS_O_SOCLDOCTL0 ) =
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( vtrim_udig << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S ) |
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( vtrim_bod << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S ) ;
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}
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// Third part of trim done after cold reset and wakeup from shutdown:
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// -Configure HPOSC.
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// -Setup the LF clock.
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#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
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SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
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#else
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NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
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#endif
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// Allow AUX to power down
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AUXWUCPowerCtrl( AUX_WUC_POWER_DOWN );
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// Leaving on AUX and clock for AUX_DDI0_OSC on but turn off clock for AUX_ADI4
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HWREG( AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0 ) = AUX_WUC_MODCLKEN0_AUX_DDI0_OSC;
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// Disable EFUSE clock
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HWREGBITW( FLASH_BASEADDR + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1;
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}
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//*****************************************************************************
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//
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//! \brief Trims to be applied when coming from PIN_RESET.
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//!
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//! \return None
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//
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//*****************************************************************************
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static void
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TrimAfterColdReset( void )
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{
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// Currently no specific trim for Cold Reset
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}
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