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450 lines
26 KiB
C
450 lines
26 KiB
C
/******************************************************************************
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* Filename: hw_flash_ctrl.h
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* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
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* Revision: $Revision: 9943 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_FLASH_CTRL_H__
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#define __HW_FLASH_CTRL_H__
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//*****************************************************************************
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//
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// The following are defines for the FLASH_CTRL register offsets.
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//
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//*****************************************************************************
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#define FLASH_CTRL_FCTL 0x400D3008 // Flash control This register
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// provides control and monitoring
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// functions for the flash module.
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#define FLASH_CTRL_FADDR 0x400D300C // Flash address The register sets
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// the address to be written in
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// flash memory. See the bitfield
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// descriptions for formatting
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// information.
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#define FLASH_CTRL_FWDATA 0x400D3010 // Flash data This register
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// contains the 32-bits of data to
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// be written to the flash location
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// selected in FADDR.
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#define FLASH_CTRL_DIECFG0 0x400D3014 // These settings are a function
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// of the FLASH information page
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// bit settings, which are
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// programmed during production
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// test, and are subject for
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// specific configuration for
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// multiple device flavors of
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// cc2538.
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#define FLASH_CTRL_DIECFG1 0x400D3018 // These settings are a function
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// of the FLASH information page
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// bit settings, which are
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// programmed during production
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// test, and are subject for
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// specific configuration for
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// multiple device flavors of
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// cc2538.
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#define FLASH_CTRL_DIECFG2 0x400D301C // These settings are a function
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// of the FLASH information page
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// bit settings, which are
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// programmed during production
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// test, and are subject for
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// specific configuration for
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// multiple device flavors of
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// cc2538. The DIE_*_REVISION
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// registers are an exeception to
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// this, as they are hardwired and
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// are not part of the FLASH
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// information page.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// FLASH_CTRL_FCTL register.
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//
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//*****************************************************************************
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#define FLASH_CTRL_FCTL_UPPER_PAGE_ACCESS \
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0x00000200 // Lock bit for lock bit page 0:
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// Neither write nor erase not
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// allowed 1: Both write and erase
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// allowed
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#define FLASH_CTRL_FCTL_UPPER_PAGE_ACCESS_M \
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0x00000200
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#define FLASH_CTRL_FCTL_UPPER_PAGE_ACCESS_S 9
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#define FLASH_CTRL_FCTL_SEL_INFO_PAGE \
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0x00000100 // Flash erase or write operation
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// on APB bus must assert this when
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// accessing the information page
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#define FLASH_CTRL_FCTL_SEL_INFO_PAGE_M \
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0x00000100
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#define FLASH_CTRL_FCTL_SEL_INFO_PAGE_S 8
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#define FLASH_CTRL_FCTL_BUSY 0x00000080 // Set when the WRITE or ERASE bit
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// is set; that is, when the flash
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// controller is busy
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#define FLASH_CTRL_FCTL_BUSY_M 0x00000080
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#define FLASH_CTRL_FCTL_BUSY_S 7
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#define FLASH_CTRL_FCTL_FULL 0x00000040 // Write buffer full The CPU can
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// write to FWDATA when this bit is
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// 0 and WRITE is 1. This bit is
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// cleared when BUSY is cleared.
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#define FLASH_CTRL_FCTL_FULL_M 0x00000040
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#define FLASH_CTRL_FCTL_FULL_S 6
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#define FLASH_CTRL_FCTL_ABORT 0x00000020 // Abort status This bit is set to
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// 1 when a write sequence or page
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// erase is aborted. An operation
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// is aborted when the accessed
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// page is locked. Cleared when a
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// write or page erase is started.
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// If a write operation times out
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// (because the FWDATA register is
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// not written fast enough), the
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// ABORT bit is not set even if the
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// page is locked. If a page erase
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// and a write operation are
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// started simultaneously, the
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// ABORT bit reflects the status of
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// the last write operation. For
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// example, if the page is locked
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// and the write times out, the
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// ABORT bit is not set because
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// only the write operation times
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// out.
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#define FLASH_CTRL_FCTL_ABORT_M 0x00000020
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#define FLASH_CTRL_FCTL_ABORT_S 5
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#define FLASH_CTRL_FCTL_CM_M 0x0000000C // Cache Mode Disabling the cache
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// increases the power consumption
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// and reduces performance.
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// Prefetching improves performance
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// at the expense of a potential
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// increase in power consumption.
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// Real-time mode provides
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// predictable flash read access
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// time, the execution time is
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// equal to cache disabled mode,
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// but the power consumption is
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// lower. 00: Cache disabled 01:
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// Cache enabled 10: Cache enabled,
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// with prefetch 11: Real-time mode
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// Note: The read value always
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// represents the current cache
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// mode. Writing a new cache mode
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// starts a cache mode change
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// request that does not take
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// effect until the controller is
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// ready. Writes to this register
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// are ignored if there is a
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// current cache change request in
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// progress.
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#define FLASH_CTRL_FCTL_CM_S 2
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#define FLASH_CTRL_FCTL_WRITE 0x00000002 // Write bit Start a write
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// sequence by setting this bit to
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// 1. Cleared by hardware when the
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// operation completes. Writes to
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// this bit are ignored when
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// FCTL.BUSY is 1. If FCTL.ERASE is
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// set simultaneously with this
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// bit, the erase operation is
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// started first, then the write is
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// started.
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#define FLASH_CTRL_FCTL_WRITE_M 0x00000002
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#define FLASH_CTRL_FCTL_WRITE_S 1
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#define FLASH_CTRL_FCTL_ERASE 0x00000001 // Erase bit Start an erase
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// operation by setting this bit to
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// 1. Cleared by hardware when the
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// operation completes. Writes to
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// this bit are ignored when
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// FCTL.BUSY is 1. If FCTL.WRITE is
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// set simultaneously with this
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// bit, the erase operation is
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// started first, then the write is
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// started.
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#define FLASH_CTRL_FCTL_ERASE_M 0x00000001
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#define FLASH_CTRL_FCTL_ERASE_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// FLASH_CTRL_FADDR register.
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//
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//*****************************************************************************
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#define FLASH_CTRL_FADDR_FADDR_M \
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0x0001FFFF // Bit number [16:9] selects one
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// of 256 pages for page erase. Bit
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// number [8:7] selects one of the
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// 4 row in a given page Bit number
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// [6:1] selects one of the 64-bit
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// wide locations in a give row.
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// Bit number [0] will select
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// upper/lower 32-bits in a given
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// 64-bit location - 64Kbytes -->
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// Bits [16:14] will always be 0. -
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// 128Kbytes --> Bits [16:15] will
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// always be 0. - 256Kbytes --> Bit
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// [16] will always be 0. -
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// 384/512Kbytes --> All bits
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// written and valid. Writes to
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// this register will be ignored
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// when any of FCTL.WRITE and
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// FCTL.ERASE is set. FADDR should
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// be written with byte addressable
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// location of the Flash to be
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// programmed. Read back value
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// always reflects a 32-bit aligned
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// address. When the register is
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// read back, the value that was
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// written to FADDR gets right
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// shift by 2 to indicate 32-bit
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// aligned address. In other words
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// lower 2 bits are discarded while
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// reading back the register. Out
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// of range address results in roll
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// over. There is no status signal
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// generated by flash controller to
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// indicate this. Firmware is
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// responsible to managing the
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// addresses correctly.
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#define FLASH_CTRL_FADDR_FADDR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// FLASH_CTRL_FWDATA register.
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//
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//*****************************************************************************
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#define FLASH_CTRL_FWDATA_FWDATA_M \
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0xFFFFFFFF // 32-bit flash write data Writes
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// to this register are accepted
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// only during a flash write
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// sequence; that is, writes to
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// this register after having
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// written 1 to the FCTL.WRITE bit.
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// New 32-bit data is written only
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// if FCTL.FULL = 0.
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#define FLASH_CTRL_FWDATA_FWDATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// FLASH_CTRL_DIECFG0 register.
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//
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//*****************************************************************************
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#define FLASH_CTRL_DIECFG0_CHIPID_M \
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0xFFFF0000 // Register copy of configuration
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// bits Three clock cycles after
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// reset is released, this bit
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// field is equal to the field with
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// the same name in the information
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// page.
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#define FLASH_CTRL_DIECFG0_CHIPID_S 16
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#define FLASH_CTRL_DIECFG0_CLK_SEL_GATE_EN_N \
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0x00000400 // Register copy of configuration
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// bits Three clock cycles after
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// reset is released, this bit is
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// equal to the field with the same
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// name in the information page.
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#define FLASH_CTRL_DIECFG0_CLK_SEL_GATE_EN_N_M \
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0x00000400
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#define FLASH_CTRL_DIECFG0_CLK_SEL_GATE_EN_N_S 10
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#define FLASH_CTRL_DIECFG0_SRAM_SIZE_M \
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0x00000380 // Register copy of configuration
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// bits Three clock cycles after
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// reset is released, this bit
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// field is equal to the field with
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// the same name in the information
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// page.
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#define FLASH_CTRL_DIECFG0_SRAM_SIZE_S 7
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#define FLASH_CTRL_DIECFG0_FLASH_SIZE_M \
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0x00000070 // Register copy of configuration
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// bits Three clock cycles after
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// reset is released, this bit
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// field is equal to the field with
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// the same name in the information
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// page.
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#define FLASH_CTRL_DIECFG0_FLASH_SIZE_S 4
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#define FLASH_CTRL_DIECFG0_USB_ENABLE \
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0x00000008 // Register copy of configuration
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// bits Three clock cycles after
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// reset is released, this bit is
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// equal to the field with the same
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// name in the information page.
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#define FLASH_CTRL_DIECFG0_USB_ENABLE_M \
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0x00000008
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#define FLASH_CTRL_DIECFG0_USB_ENABLE_S 3
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#define FLASH_CTRL_DIECFG0_MASS_ERASE_ENABLE \
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0x00000004 // Register copy of configuration
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// bits Three clock cycles after
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// reset is released, this bit is
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// equal to the field with the same
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// name in the information page.
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#define FLASH_CTRL_DIECFG0_MASS_ERASE_ENABLE_M \
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0x00000004
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#define FLASH_CTRL_DIECFG0_MASS_ERASE_ENABLE_S 2
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#define FLASH_CTRL_DIECFG0_LOCK_FWT_N \
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0x00000002 // Register copy of configuration
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// bits Three clock cycles after
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// reset is released, this bit is
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// equal to the field with the same
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// name in the information page.
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#define FLASH_CTRL_DIECFG0_LOCK_FWT_N_M \
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0x00000002
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#define FLASH_CTRL_DIECFG0_LOCK_FWT_N_S 1
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#define FLASH_CTRL_DIECFG0_LOCK_IP_N \
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0x00000001 // Register copy of configuration
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// bits Three clock cycles after
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// reset is released, this bit is
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// equal to the field with the same
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// name in the information page.
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#define FLASH_CTRL_DIECFG0_LOCK_IP_N_M \
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0x00000001
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#define FLASH_CTRL_DIECFG0_LOCK_IP_N_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// FLASH_CTRL_DIECFG1 register.
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//
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//*****************************************************************************
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#define FLASH_CTRL_DIECFG1_I2C_EN \
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0x01000000 // 1: I2C is enabled. 0: I2C is
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// permanently disabled.
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#define FLASH_CTRL_DIECFG1_I2C_EN_M \
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0x01000000
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#define FLASH_CTRL_DIECFG1_I2C_EN_S 24
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#define FLASH_CTRL_DIECFG1_UART1_EN \
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0x00020000 // 1: UART1 is enabled. 0: UART1
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// is permanently disabled.
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#define FLASH_CTRL_DIECFG1_UART1_EN_M \
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0x00020000
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#define FLASH_CTRL_DIECFG1_UART1_EN_S 17
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#define FLASH_CTRL_DIECFG1_UART0_EN \
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0x00010000 // 1: UART0 is enabled. 0: UART0
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// is permanently disabled.
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#define FLASH_CTRL_DIECFG1_UART0_EN_M \
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0x00010000
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#define FLASH_CTRL_DIECFG1_UART0_EN_S 16
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#define FLASH_CTRL_DIECFG1_SSI1_EN \
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0x00000200 // 1: SSI1 is enabled. 0: SSI1 is
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// permanently disabled.
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#define FLASH_CTRL_DIECFG1_SSI1_EN_M \
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0x00000200
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#define FLASH_CTRL_DIECFG1_SSI1_EN_S 9
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#define FLASH_CTRL_DIECFG1_SSI0_EN \
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0x00000100 // 1: SSI0 is enabled. 0: SSI0 is
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// permanently disabled.
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#define FLASH_CTRL_DIECFG1_SSI0_EN_M \
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0x00000100
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#define FLASH_CTRL_DIECFG1_SSI0_EN_S 8
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#define FLASH_CTRL_DIECFG1_GPTM3_EN \
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0x00000008 // 1: GPTM3 is enabled. 0: GPTM3
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// is permanently disabled.
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#define FLASH_CTRL_DIECFG1_GPTM3_EN_M \
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0x00000008
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#define FLASH_CTRL_DIECFG1_GPTM3_EN_S 3
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#define FLASH_CTRL_DIECFG1_GPTM2_EN \
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0x00000004 // 1: GPTM2 is enabled. 0: GPTM2
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// is permanently disabled.
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#define FLASH_CTRL_DIECFG1_GPTM2_EN_M \
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0x00000004
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#define FLASH_CTRL_DIECFG1_GPTM2_EN_S 2
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#define FLASH_CTRL_DIECFG1_GPTM1_EN \
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0x00000002 // 1: GPTM1 is enabled. 0: GPTM1
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// is permanently disabled.
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#define FLASH_CTRL_DIECFG1_GPTM1_EN_M \
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0x00000002
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#define FLASH_CTRL_DIECFG1_GPTM1_EN_S 1
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#define FLASH_CTRL_DIECFG1_GPTM0_EN \
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0x00000001 // 1: GPTM0 is enabled. 0: GPTM0
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// is permanently disabled.
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#define FLASH_CTRL_DIECFG1_GPTM0_EN_M \
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0x00000001
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#define FLASH_CTRL_DIECFG1_GPTM0_EN_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// FLASH_CTRL_DIECFG2 register.
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//
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//*****************************************************************************
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#define FLASH_CTRL_DIECFG2_DIE_MAJOR_REVISION_M \
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0x0000F000 // Indicates the major revision
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// (all layer change) number for
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// the cc2538 0x0 - PG1.0 0x2 -
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// PG2.0
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#define FLASH_CTRL_DIECFG2_DIE_MAJOR_REVISION_S 12
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#define FLASH_CTRL_DIECFG2_DIE_MINOR_REVISION_M \
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0x00000F00 // Indicates the minor revision
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// (metla layer only) number for
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// the cc2538 0x0 - PG1.0 or PG2.0
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#define FLASH_CTRL_DIECFG2_DIE_MINOR_REVISION_S 8
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#define FLASH_CTRL_DIECFG2_RF_CORE_EN \
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0x00000004 // 1: RF_CORE is enabled. 0:
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// RF_CORE is permanently disabled.
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#define FLASH_CTRL_DIECFG2_RF_CORE_EN_M \
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0x00000004
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#define FLASH_CTRL_DIECFG2_RF_CORE_EN_S 2
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#define FLASH_CTRL_DIECFG2_AES_EN \
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0x00000002 // 1: AES is enabled. 0: AES is
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// permanently disabled.
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#define FLASH_CTRL_DIECFG2_AES_EN_M \
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0x00000002
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#define FLASH_CTRL_DIECFG2_AES_EN_S 1
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#define FLASH_CTRL_DIECFG2_PKA_EN \
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0x00000001 // 1: PKA is enabled. 0: PKA is
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// permanently disabled.
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#define FLASH_CTRL_DIECFG2_PKA_EN_M \
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0x00000001
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#define FLASH_CTRL_DIECFG2_PKA_EN_S 0
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#endif // __HW_FLASH_CTRL_H__
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