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https://github.com/RIOT-OS/RIOT.git
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cd449e388b
Changed the style of the UART configuration for different boards, from a define based configuration to one based on an array of structs, one struct for each UART, with the format of the struct defined in cc2538/include/periph_cpu.h. - Defined the fields of the struct in periph_cpu.h - Removed the compilation includes that were in uart.c for each UART - Implemented a generic ISR subroutine for clarity - combined uart_base and uart_init in uart.c - used bitmask for the interrupt setup - took the uart Rx, Tx, and IRQ numbers out of the config (as this has to match the .dev field). Replaced with macros from the uart number - took out some unused code - implemented power on/off commands - removed reset function - now bytes are just discarded on error - Rx now not initialised if Rx callback = NULL, as per drivers/periph/uart.h - device is now enabled after callbacks are set, not before - asserts raised if rts and cts are enabled for UART0 - BIT macro removed
192 lines
8.3 KiB
C
192 lines
8.3 KiB
C
/*
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* Copyright (C) 2014 Loci Controls Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup cpu_cc2538_uart CC2538 UART
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* @ingroup cpu_cc2538_regs
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* @{
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*
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* @file
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* @brief CC2538 UART interface
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*
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* @author Ian Martin <ian@locicontrols.com>
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*/
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#ifndef CC2538_UART_H
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#define CC2538_UART_H
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#include "cc2538.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief UART component registers
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*/
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typedef struct {
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cc2538_reg_t DR; /**< UART Data Register */
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/**
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* @brief Status register
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*/
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union {
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cc2538_reg_t RSR; /**< UART receive status and error clear */
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cc2538_reg_t ECR; /**< UART receive status and error clear */
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} cc2538_uart_dr;
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cc2538_reg_t RESERVED1[4]; /**< Reserved addresses */
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/**
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* @brief Flag register
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*/
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union {
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cc2538_reg_t FR; /**< UART Flag Register */
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struct {
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cc2538_reg_t CTS : 1; /**< Clear to send (UART1 only) */
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cc2538_reg_t RESERVED2 : 2; /**< Reserved bits */
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cc2538_reg_t BUSY : 1; /**< UART busy */
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cc2538_reg_t RXFE : 1; /**< UART receive FIFO empty */
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cc2538_reg_t TXFF : 1; /**< UART transmit FIFO full */
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cc2538_reg_t RXFF : 1; /**< UART receive FIFO full */
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cc2538_reg_t TXFE : 1; /**< UART transmit FIFO empty */
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cc2538_reg_t RESERVED1 : 24; /**< Reserved bits */
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} FRbits;
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} cc2538_uart_fr;
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cc2538_reg_t RESERVED2; /**< Reserved byte */
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cc2538_reg_t ILPR; /**< UART IrDA Low-Power Register */
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cc2538_reg_t IBRD; /**< UART Integer Baud-Rate Divisor */
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cc2538_reg_t FBRD; /**< UART Fractional Baud-Rate Divisor */
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/**
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* @brief Line control register
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*/
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union {
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cc2538_reg_t LCRH; /**< UART Line Control Register */
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struct {
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cc2538_reg_t BRK : 1; /**< UART send break */
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cc2538_reg_t PEN : 1; /**< UART parity enable */
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cc2538_reg_t EPS : 1; /**< UART even parity select */
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cc2538_reg_t STP2 : 1; /**< UART two stop bits select */
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cc2538_reg_t FEN : 1; /**< UART enable FIFOs */
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cc2538_reg_t WLEN : 2; /**< UART word length */
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cc2538_reg_t SPS : 1; /**< UART stick parity select */
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cc2538_reg_t RESERVED : 24; /**< Reserved bits */
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} LCRHbits;
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} cc2538_uart_lcrh;
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/**
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* @brief Control register
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*/
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union {
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cc2538_reg_t CTL; /**< UART Control */
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struct {
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cc2538_reg_t UARTEN : 1; /**< UART enable */
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cc2538_reg_t SIREN : 1; /**< UART SIR enable */
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cc2538_reg_t SIRLP : 1; /**< UART SIR low-power mode */
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cc2538_reg_t RESERVED11 : 1; /**< Reserved bits */
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cc2538_reg_t EOT : 1; /**< End of transmission */
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cc2538_reg_t HSE : 1; /**< High-speed enable */
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cc2538_reg_t LIN : 1; /**< LIN mode enable */
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cc2538_reg_t LBE : 1; /**< UART loop back enable */
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cc2538_reg_t TXE : 1; /**< UART transmit enable */
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cc2538_reg_t RXE : 1; /**< UART receive enable */
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cc2538_reg_t RESERVED12 : 4; /**< Reserved bits */
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cc2538_reg_t RTSEN : 1; /**< U1RTS Hardware flow control enable */
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cc2538_reg_t CTSEN : 1; /**< U1CTS Hardware flow control enable */
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cc2538_reg_t RESERVED13 : 16; /**< Reserved bits */
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} CTLbits;
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} cc2538_uart_ctl;
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/**
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* @brief Interrupt FIFO level select register
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*/
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union {
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cc2538_reg_t IFLS; /**< UART interrupt FIFO Level Select */
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struct {
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cc2538_reg_t TXIFLSEL : 3; /**< UART transmit interrupt FIFO level select */
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cc2538_reg_t RXIFLSEL : 3; /**< UART receive interrupt FIFO level select */
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cc2538_reg_t RESERVED : 26; /**< Reserved bits */
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} IFLSbits;
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} cc2538_uart_ifls;
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/**
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* @brief Interrupt mask register
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*/
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union {
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cc2538_reg_t IM; /**< UART Interrupt Mask */
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struct {
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cc2538_reg_t RESERVED3 : 4; /**< Reserved bits */
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cc2538_reg_t RXIM : 1; /**< UART receive interrupt mask */
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cc2538_reg_t TXIM : 1; /**< UART transmit interrupt mask */
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cc2538_reg_t RTIM : 1; /**< UART receive time-out interrupt mask */
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cc2538_reg_t FEIM : 1; /**< UART framing error interrupt mask */
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cc2538_reg_t PEIM : 1; /**< UART parity error interrupt mask */
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cc2538_reg_t BEIM : 1; /**< UART break error interrupt mask */
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cc2538_reg_t OEIM : 1; /**< UART overrun error interrupt mask */
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cc2538_reg_t RESERVED2 : 1; /**< Reserved bits */
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cc2538_reg_t NINEBITM : 1; /**< 9-bit mode interrupt mask */
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cc2538_reg_t LMSBIM : 1; /**< LIN mode sync break interrupt mask */
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cc2538_reg_t LME1IM : 1; /**< LIN mode edge 1 interrupt mask */
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cc2538_reg_t LME5IM : 1; /**< LIN mode edge 5 interrupt mask */
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cc2538_reg_t RESERVED1 : 16; /**< Reserved bits */
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} IMbits;
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} cc2538_uart_im;
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cc2538_reg_t RIS; /**< UART Raw Interrupt Status */
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/**
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* @brief Masked interrupt status register
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*/
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union {
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cc2538_reg_t MIS; /**< UART Masked Interrupt Status */
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struct {
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cc2538_reg_t RESERVED8 : 4; /**< Reserved bits */
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cc2538_reg_t RXMIS : 1; /**< UART receive masked interrupt status */
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cc2538_reg_t TXMIS : 1; /**< UART transmit masked interrupt status */
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cc2538_reg_t RTMIS : 1; /**< UART receive time-out masked interrupt status */
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cc2538_reg_t FEMIS : 1; /**< UART framing error masked interrupt status */
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cc2538_reg_t PEMIS : 1; /**< UART parity error masked interrupt status */
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cc2538_reg_t BEMIS : 1; /**< UART break error masked interrupt status */
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cc2538_reg_t OEMIS : 1; /**< UART overrun error masked interrupt status */
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cc2538_reg_t RESERVED9 : 1; /**< Reserved bits */
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cc2538_reg_t NINEBITMIS : 1; /**< 9-bit mode masked interrupt status */
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cc2538_reg_t LMSBMIS : 1; /**< LIN mode sync break masked interrupt status */
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cc2538_reg_t LME1MIS : 1; /**< LIN mode edge 1 masked interrupt status */
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cc2538_reg_t LME5MIS : 1; /**< LIN mode edge 5 masked interrupt status */
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cc2538_reg_t RESERVED10 : 16; /**< Reserved bits */
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} MISbits;
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} cc2538_uart_mis;
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cc2538_reg_t ICR; /**< UART Interrupt Clear Register */
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cc2538_reg_t DMACTL; /**< UART DMA Control */
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cc2538_reg_t RESERVED3[17]; /**< Reserved addresses */
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cc2538_reg_t LCTL; /**< UART LIN Control */
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cc2538_reg_t LSS; /**< UART LIN Snap Shot */
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cc2538_reg_t LTIM; /**< UART LIN Timer */
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cc2538_reg_t RESERVED4[2]; /**< Reserved addresses */
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cc2538_reg_t NINEBITADDR; /**< UART 9-bit self Address */
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cc2538_reg_t NINEBITAMASK; /**< UART 9-bit self Address Mask */
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cc2538_reg_t RESERVED5[965]; /**< Reserved addresses */
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cc2538_reg_t PP; /**< UART Peripheral Properties */
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cc2538_reg_t RESERVED6; /**< Reserved addresses */
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cc2538_reg_t CC; /**< UART Clock Configuration */
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cc2538_reg_t RESERVED7[13]; /**< Reserved addresses */
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} cc2538_uart_t;
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#define UART0_BASEADDR (cc2538_uart_t *)(&UART0_DR) /**< UART0 Instance */
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#define UART1_BASEADDR (cc2538_uart_t *)(&UART1_DR) /**< UART1 Instance */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* CC2538_UART_H */
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/** @} */
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