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https://github.com/RIOT-OS/RIOT.git
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e381317fbf
cpu, nrf5x_common: fix sign-compare in periph/flashpage
drivers, periph_common: fix sign-compare in flashpage
cpu, sam0_common: fix sign-compare error in periph/gpio
cpu, cc2538: fix sign-compare in periph/timer
cpu, sam3: fix sign-compare in periph/gpio
cpu, stm32_common: fix sign-compare in periph/pwm
cpu, stm32_common: fix sign-compare in periph/timer
cpu, stm32_common: fix sign-compare in periph/flashpage
cpu, nrf5x_common: fix sign-compare in radio/nrfmin
cpu, samd21: fix sign-compare in periph/pwm
cpu, ezr32wg: fix sign-compare in periph/gpio
cpu, ezr32wg: fix sign-compare in periph/timer
drivers, ethos: fix sign-compare
sys, net: fix sign-compare
cpu, atmega_common: fix sign-compare error
cpu, msp430fxyz: fix sign-compare in periph/gpio
boards, msb-430-common: fix sign-compare in board_init
driver, cc2420: fix sign-compared
sys/net: fix sign-compare in gnrc_tftp
driver, pcd8544: fix sign-compare
driver, pn532: fix sign-compare
driver, sdcard_spi: fix sign-compare
tests: fix sign_compare
sys/net, lwmac: fix sign_compare
pkg, lwip: fix sign-compare
boards, waspmote: make CORECLOCK unsigned long to fix sign_compare error
tests, sock_ip: fix sign compare
tests, msg_avail: fix sign compare
tests, sock_udp: fix sign compare
boards: fix sign-compare for calliope and microbit matrix
166 lines
8.1 KiB
C
166 lines
8.1 KiB
C
/*
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* Copyright (C) 2014 Loci Controls Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup cpu_cc2538_sysctrl CC2538 System Control
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* @ingroup cpu_cc2538_regs
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* @{
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*
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* @file
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* @brief CC2538 System Control interface
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*
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* @author Ian Martin <ian@locicontrols.com>
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*/
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#ifndef CC2538_SYS_CTRL_H
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#define CC2538_SYS_CTRL_H
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#include "cc2538.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief System Control component registers
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*/
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typedef struct {
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/**
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* @brief Clock control register
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*/
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union {
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cc2538_reg_t CLOCK_CTRL; /**< Clock control register */
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struct {
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cc2538_reg_t SYS_DIV : 3; /**< System clock rate setting */
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cc2538_reg_t RESERVED1 : 5; /**< Reserved bits */
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cc2538_reg_t IO_DIV : 3; /**< I/O clock rate setting */
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cc2538_reg_t RESERVED2 : 5; /**< Reserved bits */
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cc2538_reg_t OSC : 1; /**< System clock oscillator selection */
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cc2538_reg_t OSC_PD : 1; /**< Oscillator power-down */
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cc2538_reg_t RESERVED3 : 3; /**< Reserved bits */
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cc2538_reg_t AMP_DET : 1; /**< Amplitude detector of XOSC during power up */
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cc2538_reg_t RESERVED4 : 2; /**< Reserved bits */
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cc2538_reg_t OSC32K : 1; /**< 32-kHz clock oscillator selection */
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cc2538_reg_t OSC32K_CADIS : 1; /**< Disable calibration 32-kHz RC oscillator */
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cc2538_reg_t RESERVED5 : 6; /**< Reserved bits */
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} CLOCK_CTRLbits;
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} cc2538_sys_ctrl_clk_ctrl;
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/**
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* @brief Clock status register
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*/
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union {
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cc2538_reg_t CLOCK_STA; /**< Clock status register */
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struct {
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cc2538_reg_t SYS_DIV : 3; /**< Current functional frequency for system clock */
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cc2538_reg_t RESERVED6 : 5; /**< Reserved bits */
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cc2538_reg_t IO_DIV : 3; /**< Current functional frequency for IO_CLK */
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cc2538_reg_t RESERVED7 : 5; /**< Reserved bits */
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cc2538_reg_t OSC : 1; /**< Current clock source selected */
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cc2538_reg_t OSC_PD : 1; /**< Oscillator power-down */
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cc2538_reg_t HSOSC_STB : 1; /**< HSOSC stable status */
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cc2538_reg_t XOSC_STB : 1; /**< XOSC stable status */
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cc2538_reg_t SOURCE_CHANGE : 1; /**< System clock source change */
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cc2538_reg_t RESERVED8 : 1; /**< Reserved bits */
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cc2538_reg_t RST : 2; /**< Last source of reset */
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cc2538_reg_t OSC32K : 1; /**< Current 32-kHz clock oscillator selected */
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cc2538_reg_t OSC32K_CALDIS : 1; /**< Disable calibration 32-kHz RC oscillator */
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cc2538_reg_t SYNC_32K : 1; /**< 32-kHz clock source synced to undivided system clock (16 or 32 MHz) */
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cc2538_reg_t RESERVED9 : 5; /**< Reserved bits */
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} CLOCK_STAbits;
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} cc2538_sys_ctrl_clk_sta;
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cc2538_reg_t RCGCGPT; /**< Module clocks for GPT[3:0] when the CPU is in active (run) mode */
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cc2538_reg_t SCGCGPT; /**< Module clocks for GPT[3:0] when the CPU is in sleep mode */
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cc2538_reg_t DCGCGPT; /**< Module clocks for GPT[3:0] when the CPU is in PM0 */
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cc2538_reg_t SRGPT; /**< Reset for GPT[3:0]. */
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cc2538_reg_t RCGCSSI; /**< Module clocks for SSI[1:0] when the CPU is in active (run) mode */
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cc2538_reg_t SCGCSSI; /**< Module clocks for SSI[1:0] when the CPU is insSleep mode */
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cc2538_reg_t DCGCSSI; /**< Module clocks for SSI[1:0] when the CPU is in PM0 */
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cc2538_reg_t SRSSI; /**< Reset for SSI[1:0]. */
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/**
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* @brief UART module clock register - active mode
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*/
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union {
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cc2538_reg_t RCGCUART; /**< Module clocks for UART[1:0] when the CPU is in active (run) mode */
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struct {
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cc2538_reg_t UART0 : 1; /**< Enable UART0 clock in active (run) mode */
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cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in active (run) mode */
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cc2538_reg_t RESERVED : 30; /**< Reserved bits */
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} RCGCUARTbits;
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} cc2538_sys_ctrl_unnamed1;
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/**
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* @brief UART module clock register - sleep mode
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*/
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union {
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cc2538_reg_t SCGCUART; /**< Module clocks for UART[1:0] when the CPU is in sleep mode */
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struct {
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cc2538_reg_t UART0 : 1; /**< Enable UART0 clock in sleep mode */
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cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in sleep mode */
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cc2538_reg_t RESERVED : 30; /**< Reserved bits */
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} SCGCUARTbits;
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} cc2538_sys_ctrl_unnamed2;
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/**
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* @brief UART module clock register - PM0 mode
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*/
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union {
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cc2538_reg_t DCGCUART; /**< Module clocks for UART[1:0] when the CPU is in PM0 */
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struct {
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cc2538_reg_t UART0 : 1; /**< Enable UART0 clock in PM0 */
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cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in PM0 */
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cc2538_reg_t RESERVED : 30; /**< Reserved bits */
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} DCGCUARTbits;
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} cc2538_sys_ctrl_unnamed3;
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cc2538_reg_t SRUART; /**< Reset for UART[1:0]. */
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cc2538_reg_t RCGCI2C; /**< Module clocks for I2C when the CPU is in active (run) mode */
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cc2538_reg_t SCGCI2C; /**< Module clocks for I2C when the CPU is in sleep mode */
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cc2538_reg_t DCGCI2C; /**< Module clocks for I2C when the CPU is in PM0 */
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cc2538_reg_t SRI2C; /**< Reset for I2C. */
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cc2538_reg_t RCGCSEC; /**< Module clocks for the security module when the CPU is in active (run) mode */
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cc2538_reg_t SCGCSEC; /**< Module clocks for the security module when the CPU is in sleep mode */
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cc2538_reg_t DCGCSEC; /**< Module clocks for the security module when the CPU is in PM0 */
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cc2538_reg_t SRSEC; /**< Reset for the security module. */
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cc2538_reg_t PMCTL; /**< Power mode. */
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cc2538_reg_t SRCRC; /**< CRC on state retention. */
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cc2538_reg_t RESERVED10[5]; /**< Reserved bits */
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cc2538_reg_t PWRDBG; /**< Power debug register */
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cc2538_reg_t RESERVED11[2]; /**< Reserved bits */
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cc2538_reg_t CLD; /**< This register controls the clock loss detection feature. */
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cc2538_reg_t RESERVED12[4]; /**< Reserved bits */
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cc2538_reg_t IWE; /**< This register controls interrupt wake-up. */
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cc2538_reg_t I_MAP; /**< This register selects which interrupt map to be used. */
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cc2538_reg_t RESERVED13[3]; /**< Reserved bits */
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cc2538_reg_t RCGCRFC; /**< This register defines the module clocks for RF CORE when the CPU is in active (run) mode */
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cc2538_reg_t SCGCRFC; /**< This register defines the module clocks for RF CORE when the CPU is in sleep mode */
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cc2538_reg_t DCGCRFC; /**< This register defines the module clocks for RF CORE when the CPU is in PM0 */
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cc2538_reg_t EMUOVR; /**< This register defines the emulator override controls for power mode and peripheral clock gate. */
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} cc2538_sys_ctrl_t;
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#define SYS_CTRL ( (cc2538_sys_ctrl_t*)0x400d2000 ) /**< One and only instance of the System Control module */
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/**
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* @brief Compute the current system clock frequency based on the SYS_CTRL register states
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*/
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#define sys_clock_freq() ((uint32_t)\
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(SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC ? \
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RCOSC16M_FREQ : XOSC32M_FREQ) >> \
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.SYS_DIV)
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* CC2538_SYS_CTRL_H */
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/** @} */
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