mirror of
https://github.com/RIOT-OS/RIOT.git
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198 lines
8.6 KiB
C
198 lines
8.6 KiB
C
/*
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* Copyright (C) 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_stm32f769i-disco
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the STM32F769I-DISCO board
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* This board provides an LSE */
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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/* The HSE provides a 25MHz clock */
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#ifndef CONFIG_CLOCK_HSE
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#define CONFIG_CLOCK_HSE MHZ(25)
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#endif
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#include "periph_cpu.h"
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#include "clk_conf.h"
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#include "cfg_rtt_default.h"
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#include "cfg_timer_tim2.h"
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#include "cfg_usb_otg_fs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn,
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}
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};
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#define UART_0_ISR (isr_usart1)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name FMC configuration
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* @{
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*/
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/**
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* @brief FMC controller configuration
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*/
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static const fmc_conf_t fmc_config = {
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.bus = AHB3,
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.rcc_mask = RCC_AHB3ENR_FMCEN,
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#if MODULE_PERIPH_FMC_SDRAM
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.ba0_pin = { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* FMC_BA0 signal */
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.ba1_pin = { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* FMC_BA1 signal */
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.sdclk_pin = { .pin = GPIO_PIN(PORT_G, 8), .af = GPIO_AF12, }, /* FMC_SDCLK signal */
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.sdnwe_pin = { .pin = GPIO_PIN(PORT_H, 5), .af = GPIO_AF12, }, /* FMC_SDNWE signal */
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.sdnras_pin = { .pin = GPIO_PIN(PORT_F, 11), .af = GPIO_AF12, }, /* FMC_SDNRAS signal */
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.sdncas_pin = { .pin = GPIO_PIN(PORT_G, 15), .af = GPIO_AF12, }, /* FMC_SDNCAS signal */
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.sdcke0_pin = { .pin = GPIO_PIN(PORT_H, 2), .af = GPIO_AF12, }, /* FMC_SDCKE0 signal */
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.sdne0_pin = { .pin = GPIO_PIN(PORT_H, 3), .af = GPIO_AF12, }, /* FMC_SDNE0 signal */
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.addr = {
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{ .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* FMC_A0 signal */
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{ .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* FMC_A1 signal */
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{ .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* FMC_A2 signal */
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{ .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* FMC_A3 signal */
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{ .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* FMC_A4 signal */
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{ .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* FMC_A5 signal */
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{ .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* FMC_A6 signal */
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{ .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* FMC_A7 signal */
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{ .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* FMC_A8 signal */
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{ .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* FMC_A9 signal */
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{ .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* FMC_A10 signal */
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{ .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* FMC_A11 signal */
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},
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#endif
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.data = {
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{ .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* FMC_D0 signal */
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{ .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* FMC_D1 signal */
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{ .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* FMC_D2 signal */
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{ .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* FMC_D3 signal */
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{ .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* FMC_D4 signal */
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{ .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* FMC_D5 signal */
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{ .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* FMC_D6 signal */
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{ .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* FMC_D7 signal */
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#if MODULE_PERIPH_FMC_32BIT
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{ .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* FMC_D8 signal */
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{ .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* FMC_D9 signal */
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{ .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* FMC_D10 signal */
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{ .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* FMC_D11 signal */
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{ .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* FMC_D12 signal */
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{ .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* FMC_D13 signal */
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{ .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* FMC_D14 signal */
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{ .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* FMC_D15 signal */
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{ .pin = GPIO_PIN(PORT_H, 8), .af = GPIO_AF12, }, /* FMC_D16 signal */
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{ .pin = GPIO_PIN(PORT_H, 9), .af = GPIO_AF12, }, /* FMC_D17 signal */
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{ .pin = GPIO_PIN(PORT_H, 10), .af = GPIO_AF12, }, /* FMC_D18 signal */
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{ .pin = GPIO_PIN(PORT_H, 11), .af = GPIO_AF12, }, /* FMC_D19 signal */
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{ .pin = GPIO_PIN(PORT_H, 12), .af = GPIO_AF12, }, /* FMC_D20 signal */
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{ .pin = GPIO_PIN(PORT_H, 13), .af = GPIO_AF12, }, /* FMC_D21 signal */
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{ .pin = GPIO_PIN(PORT_H, 14), .af = GPIO_AF12, }, /* FMC_D22 signal */
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{ .pin = GPIO_PIN(PORT_H, 15), .af = GPIO_AF12, }, /* FMC_D23 signal */
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{ .pin = GPIO_PIN(PORT_I, 0), .af = GPIO_AF12, }, /* FMC_D24 signal */
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{ .pin = GPIO_PIN(PORT_I, 1), .af = GPIO_AF12, }, /* FMC_D25 signal */
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{ .pin = GPIO_PIN(PORT_I, 2), .af = GPIO_AF12, }, /* FMC_D26 signal */
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{ .pin = GPIO_PIN(PORT_I, 3), .af = GPIO_AF12, }, /* FMC_D27 signal */
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{ .pin = GPIO_PIN(PORT_I, 6), .af = GPIO_AF12, }, /* FMC_D28 signal */
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{ .pin = GPIO_PIN(PORT_I, 7), .af = GPIO_AF12, }, /* FMC_D29 signal */
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{ .pin = GPIO_PIN(PORT_I, 9), .af = GPIO_AF12, }, /* FMC_D30 signal */
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{ .pin = GPIO_PIN(PORT_I, 10), .af = GPIO_AF12, }, /* FMC_D31 signal */
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#endif
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},
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.nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* FMC_NBL0 signal (DQM0) */
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.nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* FMC_NBL1 signal (DQM1) */
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.nbl2_pin = { .pin = GPIO_PIN(PORT_I, 4), .af = GPIO_AF12, }, /* FMC_NBL2 signal (DQM2) */
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.nbl3_pin = { .pin = GPIO_PIN(PORT_I, 5), .af = GPIO_AF12, }, /* FMC_NBL3 signal (DQM3) */
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};
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/**
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* @brief FMC Bank configuration
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*
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* The board has a SDRAM MT48LC4M32B2B5-6A with 128 MBit on-board.
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* It is organized in 4 banks of 1M x 32 bits each and connected to bank 5
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* at address 0xc0000000.
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*/
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static const fmc_bank_conf_t fmc_bank_config[] = {
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/* bank 5 is used for SDRAM */
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{
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.bank = FMC_BANK_5,
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.mem_type = FMC_SDRAM,
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.data_width = FMC_BUS_WIDTH_32BIT,
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.address = 0xc0000000, /* Bank 6 is mapped to 0xc0000000 */
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.size = MiB(16), /* Size in MByte, 4M x 32 Bit */
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.sdram = {
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.clk_period = 2, /* SDCLK = 2 x HCLK */
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.row_bits = 12, /* A11..A0 used for row address */
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.col_bits = 8, /* A7..A0 used for column address */
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.cas_latency = 2, /* CAS latency is 2 clock cycles */
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.read_delay = 0, /* No read delay after CAS */
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.burst_read = true, /* Burst read mode enabled */
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.burst_write = false, /* Burst write mode disabled */
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.burst_len = FMC_BURST_LENGTH_1, /* Burst length is 1 */
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.burst_interleaved = false, /* Burst mode interleaved */
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.write_protect = false, /* No write protection */
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.four_banks = true, /* SDRAM has four internal banks */
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.timing = { /* SDRAM Timing parameters */
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.row_to_col_delay = 2, /* Row to column delay (2 clock cycles) */
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.row_precharge = 2, /* Row precharge delay (2 clock cycles) */
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.recovery_delay = 2, /* Recovery delay is (2 clock cycles) */
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.row_cylce = 7, /* Row cycle delay is (7 clock cycles) */
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.self_refresh = 4, /* Self refresh time is (4 clock cycles) */
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.exit_self_refresh = 7, /* Exit self-refresh delay (7 clock cycles) */
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.load_mode_register = 2, /* Load Mode Register to Activate delay */
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.refresh_period = 64, /* Refresh period in ms */
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},
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},
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},
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};
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/**
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* @brief Number of configured FMC banks
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*/
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#define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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