mirror of
https://github.com/RIOT-OS/RIOT.git
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05f114d0af
- most were trivial
- missing group close or open
- extra space
- no doxygen comment
- name commad might open an implicit group
this hould also be implicit cosed but does not happen somtimes
- crazy: internal declared groups have to be closed internal
149 lines
3.3 KiB
C
149 lines
3.3 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_stm32f0discovery
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the STM32F0discovery board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "clk_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_B, 7),
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.tx_pin = GPIO_PIN(PORT_B, 6),
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.rx_af = GPIO_AF0,
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.tx_af = GPIO_AF0,
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.bus = APB2,
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.irqn = USART1_IRQn,
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},
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF1,
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.tx_af = GPIO_AF1,
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.bus = APB1,
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.irqn = USART2_IRQn
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}
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};
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#define UART_0_ISR (isr_usart1)
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#define UART_1_ISR (isr_usart2)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name ADC configuration
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*
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* We need to configure the following values:
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* [ pin, channel ]
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* @{
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*/
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static const adc_conf_t adc_config[] = {
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{ GPIO_PIN(PORT_C, 0), 10 },
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{ GPIO_PIN(PORT_C, 1), 11 },
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{ GPIO_PIN(PORT_C, 2), 12 },
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{ GPIO_PIN(PORT_C, 3), 13 },
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{ GPIO_PIN(PORT_C, 4), 14 },
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{ GPIO_PIN(PORT_C, 5), 15 },
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{ GPIO_UNDEF, 18 }, /* VBAT */
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};
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#define VBAT_ADC ADC_LINE(6) /**< VBAT ADC line */
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#define ADC_NUMOF ARRAY_SIZE(adc_config)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = SPI_CS_UNDEF,
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.mosi_af = GPIO_AF0,
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.miso_af = GPIO_AF0,
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.sclk_af = GPIO_AF0,
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.cs_af = GPIO_AF0,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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},
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{
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.dev = SPI2,
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.mosi_pin = GPIO_PIN(PORT_B, 15),
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.miso_pin = GPIO_PIN(PORT_B, 14),
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.sclk_pin = GPIO_PIN(PORT_B, 13),
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.cs_pin = SPI_CS_UNDEF,
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.mosi_af = GPIO_AF0,
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.miso_af = GPIO_AF0,
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.sclk_af = GPIO_AF0,
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.cs_af = GPIO_AF0,
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.rccmask = RCC_APB1ENR_SPI2EN,
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.apbbus = APB1
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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