mirror of
https://github.com/RIOT-OS/RIOT.git
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df37e69b90
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
492 lines
32 KiB
C
Executable File
492 lines
32 KiB
C
Executable File
/******************************************************************************
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* Filename: hw_ssi.h
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* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
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* Revision: $Revision: 9943 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_SSI_H__
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#define __HW_SSI_H__
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//*****************************************************************************
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//
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// The following are defines for the SSI register offsets.
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//
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//*****************************************************************************
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#define SSI_O_CR0 0x00000000 // The CR0 register contains bit
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// fields that control various
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// functions within the SSI module.
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// Functionality such as protocol
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// mode, clock rate, and data size
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// are configured in this register.
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#define SSI_O_CR1 0x00000004 // The CR1 register contains bit
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// fields that control various
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// functions within the SSI module.
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// Master and slave mode
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// functionality is controlled by
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// this register.
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#define SSI_O_DR 0x00000008 // The DR register is 16 bits
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// wide. When the SSIDR register is
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// read, the entry in the receive
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// FIFO that is pointed to by the
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// current FIFO read pointer is
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// accessed. When a data value is
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// removed by the SSI receive logic
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// from the incoming data frame, it
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// is placed into the entry in the
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// receive FIFO pointed to by the
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// current FIFO write pointer. When
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// the DR register is written to,
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// the entry in the transmit FIFO
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// that is pointed to by the write
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// pointer is written to. Data
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// values are removed from the
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// transmit FIFO one value at a
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// time by the transmit logic. Each
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// data value is loaded into the
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// transmit serial shifter, then
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// serially shifted out onto the
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// SSITx pin at the programmed bit
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// rate. When a data size of less
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// than 16 bits is selected, the
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// user must right-justify data
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// written to the transmit FIFO.
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// The transmit logic ignores the
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// unused bits. Received data less
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// than 16 bits is automatically
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// right-justified in the receive
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// buffer. When the SSI is
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// programmed for MICROWIRE frame
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// format, the default size for
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// transmit data is eight bits (the
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// most significant byte is
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// ignored). The receive data size
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// is controlled by the programmer.
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// The transmit FIFO and the
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// receive FIFO are not cleared
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// even when the SSE bit in the
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// SSICR1 register is cleared,
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// allowing the software to fill
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// the transmit FIFO before
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// enabling the SSI.
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#define SSI_O_SR 0x0000000C // The SR register contains bits
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// that indicate the FIFO fill
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// status and the SSI busy status.
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#define SSI_O_CPSR 0x00000010 // The CPSR register specifies the
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// division factor which is used to
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// derive the SSIClk from the
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// system clock. The clock is
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// further divided by a value from
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// 1 to 256, which is 1 + SCR. SCR
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// is programmed in the SSICR0
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// register. The frequency of the
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// SSIClk is defined by: SSIClk =
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// SysClk / (CPSDVSR x (1 + SCR))
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// The value programmed into this
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// register must be an even number
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// between 2 and 254. The
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// least-significant bit of the
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// programmed number is hard-coded
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// to zero. If an odd number is
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// written to this register, data
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// read back from this register has
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// the least-significant bit as
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// zero.
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#define SSI_O_IM 0x00000014 // The IM register is the
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// interrupt mask set or clear
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// register. It is a read/write
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// register and all bits are
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// cleared on reset. On a read,
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// this register gives the current
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// value of the mask on the
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// corresponding interrupt. Setting
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// a bit sets the mask, preventing
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// the interrupt from being
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// signaled to the interrupt
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// controller. Clearing a bit
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// clears the corresponding mask,
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// enabling the interrupt to be
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// sent to the interrupt
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// controller.
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#define SSI_O_RIS 0x00000018 // The RIS register is the raw
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// interrupt status register. On a
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// read, this register gives the
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// current raw status value of the
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// corresponding interrupt before
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// masking. A write has no effect.
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#define SSI_O_MIS 0x0000001C // The MIS register is the masked
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// interrupt status register. On a
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// read, this register gives the
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// current masked status value of
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// the corresponding interrupt. A
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// write has no effect.
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#define SSI_O_ICR 0x00000020 // The ICR register is the
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// interrupt clear register. On a
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// write of 1, the corresponding
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// interrupt is cleared. A write of
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// 0 has no effect.
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#define SSI_O_DMACTL 0x00000024 // The DMACTL register is the uDMA
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// control register.
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#define SSI_O_CC 0x00000FC8 // SSI clock configuration The CC
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// register controls the baud clock
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// and system clocks sources for
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// the SSI module. Note: If the
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// PIOSC is used for the SSI baud
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// clock, the system clock
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// frequency must be at least 16
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// MHz in run mode.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_CR0 register.
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//
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//*****************************************************************************
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#define SSI_CR0_SCR_M 0x0000FF00 // SSI serial clock rate (R/W)
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// Reset value: 0x0 The value SCR
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// is used to generate the transmit
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// and receive bit rate of the SSI.
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// Where the bit rate is: BR =
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// FSSICLK/(CPSDVR * (1 + SCR))
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// where CPSDVR is an even value
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// from 2-254, programmed in the
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// SSICPSR register and SCR is a
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// value from 0-255.
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#define SSI_CR0_SCR_S 8
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#define SSI_CR0_SPH 0x00000080 // SSI serial clock phase (R/W)
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// Reset value: 0x0 This bit is
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// only applicable to the Motorola
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// SPI Format.
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#define SSI_CR0_SPH_M 0x00000080
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#define SSI_CR0_SPH_S 7
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#define SSI_CR0_SPO 0x00000040 // SSI serial clock phase (R/W)
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// Reset value: 0x0 This bit is
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// only applicable to the Motorola
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// SPI Format.
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#define SSI_CR0_SPO_M 0x00000040
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#define SSI_CR0_SPO_S 6
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#define SSI_CR0_FRF_M 0x00000030 // SSI frame format select (R/W)
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// Reset value: 0x0 00: Motorola
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// SPI frame format 01: TI
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// synchronous serial frame format
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// 10: National Microwire frame
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// format 11: Reserved
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#define SSI_CR0_FRF_S 4
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#define SSI_CR0_DSS_M 0x0000000F // SSI data size select (R/W)
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// Reset value: 0x0 0000-0010:
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// Reserved 0011: 4-bit data 0100:
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// 5-bit data 0101: 6-bit data
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// 0110: 7-bit data 0111: 8-bit
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// data 1000: 9-bit data 1001:
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// 10-bit data 1010: 11-bit data
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// 1011: 12-bit data 1100: 13-bit
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// data 1101: 14-bit data 1110:
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// 15-bit data 1111: 16-bit data
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#define SSI_CR0_DSS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_CR1 register.
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//
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//*****************************************************************************
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#define SSI_CR1_SOD 0x00000008 // SSI slave mode output disable
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// (R/W) Reset value: 0x0 This bit
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// is relevant only in the slave
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// mode (MS = 1). In multiple-slave
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// systems, it is possible for the
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// SSI master to broadcast a
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// message to all slaves in the
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// system while ensuring that only
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// one slave drives data onto the
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// serial output line. In such
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// systems, the RXD lines from
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// multiple slaves could be tied
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// together. To operate in such a
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// system, the SOD bit can be set
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// if the SSI slave is not suppose
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// to drive the SSITXD line. 0: SSI
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// can drive SSITXD in slave output
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// mode 1: SSI must not drive the
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// SSITXD output in slave mode
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#define SSI_CR1_SOD_M 0x00000008
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#define SSI_CR1_SOD_S 3
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#define SSI_CR1_MS 0x00000004 // SSI master and slave select
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// (R/W) Reset value: 0x0 This bit
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// can be modified only when the
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// SSI is disabled (SSE = 0). 0:
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// Device configured as a master
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// (default) 1: Device configured
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// as a slave
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#define SSI_CR1_MS_M 0x00000004
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#define SSI_CR1_MS_S 2
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#define SSI_CR1_SSE 0x00000002 // SSI synchronous serial port
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// enable (R/W) Reset value: 0x0 0:
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// SSI operation is disabled. 1:
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// SSI operation is enabled.
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#define SSI_CR1_SSE_M 0x00000002
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#define SSI_CR1_SSE_S 1
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#define SSI_CR1_LBM 0x00000001 // SSI loop-back mode (R/W) Reset
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// value: 0x0 0: Normal serial port
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// operation is enabled. 1: The
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// output of the transmit serial
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// shifter is connected to the
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// input of the receive serial
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// shift register internally.
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#define SSI_CR1_LBM_M 0x00000001
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#define SSI_CR1_LBM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_DR register.
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//
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//*****************************************************************************
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#define SSI_DR_DATA_M 0x0000FFFF // SSI receive/transmit data
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// register (R/W) Reset value:
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// 0xXXXX A read operation reads
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// the receive FIFO. A write
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// operation writes the transmit
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// FIFO. Software must
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// right-justify data when the SSI
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// is programmed for a data size
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// that is less than 16 bits.
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// Unused bits at the top are
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// ignored by the transmit logic.
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// The receive logic automatically
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// right-justified the data.
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#define SSI_DR_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_SR register.
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//
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//*****************************************************************************
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#define SSI_SR_BSY 0x00000010 // SSI busy bit (RO) Reset value:
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// 0x0 0: SSI is idle. 1: SSI is
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// currently transmitting and/or
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// receiving a frame or the
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// transmit FIFO is not empty.
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#define SSI_SR_BSY_M 0x00000010
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#define SSI_SR_BSY_S 4
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#define SSI_SR_RFF 0x00000008 // SSI receive FIFO full (RO)
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// Reset value: 0x0 0: Receive FIFO
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// is not full. 1: Receive FIFO is
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// full.
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#define SSI_SR_RFF_M 0x00000008
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#define SSI_SR_RFF_S 3
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#define SSI_SR_RNE 0x00000004 // SSI receive FIFO not empty (RO)
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// Reset value: 0x0 0: Receive FIFO
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// is empty. 1: Receive FIFO is not
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// empty.
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#define SSI_SR_RNE_M 0x00000004
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#define SSI_SR_RNE_S 2
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#define SSI_SR_TNF 0x00000002 // SSI transmit FIFO not full (RO)
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// Reset value: 0x1 0: Transmit
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// FIFO is full. 1: Transmit FIFO
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// is not full.
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#define SSI_SR_TNF_M 0x00000002
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#define SSI_SR_TNF_S 1
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#define SSI_SR_TFE 0x00000001 // SSI transmit FIFO empty (RO)
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// Reset value: 0x1 0: Transmit
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// FIFO is not empty. 1: Transmit
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// FIFO is empty.
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#define SSI_SR_TFE_M 0x00000001
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#define SSI_SR_TFE_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_CPSR register.
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//
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//*****************************************************************************
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#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI clock prescale divisor
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// (R/W) Reset value: 0x0 This
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// value must be an even number
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// from 2 to 254, depending on the
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// frequency of SSICLK. The LSB
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// always returns zero on reads.
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#define SSI_CPSR_CPSDVSR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_IM register.
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//
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//*****************************************************************************
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#define SSI_IM_TXIM 0x00000008 // SSI transmit FIFO interrupt
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// mask (R/W) Reset value: 0x0 0:
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// TX FIFO half empty or condition
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// interrupt is masked. 1: TX FIFO
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// half empty or less condition
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// interrupt is not masked.
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#define SSI_IM_TXIM_M 0x00000008
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#define SSI_IM_TXIM_S 3
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#define SSI_IM_RXIM 0x00000004 // SSI receive FIFO interrupt mask
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// (R/W) Reset value: 0x0 0: RX
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// FIFO half empty or condition
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// interrupt is masked. 1: RX FIFO
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// half empty or less condition
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// interrupt is not masked.
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#define SSI_IM_RXIM_M 0x00000004
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#define SSI_IM_RXIM_S 2
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#define SSI_IM_RTIM 0x00000002 // SSI receive time-out interrupt
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// mask (R/W) Reset value: 0x0 0:
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// RX FIFO time-out interrupt is
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// masked. 1: RX FIFO time-out
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// interrupt is not masked
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#define SSI_IM_RTIM_M 0x00000002
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#define SSI_IM_RTIM_S 1
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#define SSI_IM_RORIM 0x00000001 // SSI receive overrun interrupt
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// mask (R/W) Reset value: 0x0 0:
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// RX FIFO Overrun interrupt is
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// masked. 1: RX FIFO Overrun
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// interrupt is not masked
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#define SSI_IM_RORIM_M 0x00000001
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#define SSI_IM_RORIM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_RIS register.
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//
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//*****************************************************************************
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#define SSI_RIS_TXRIS 0x00000008 // SSI SSITXINTR raw state (RO)
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// Reset value: 0x1 Gives the raw
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// interrupt state (before masking)
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// of SSITXINTR
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#define SSI_RIS_TXRIS_M 0x00000008
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#define SSI_RIS_TXRIS_S 3
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#define SSI_RIS_RXRIS 0x00000004 // SSI SSIRXINTR raw state (RO)
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// Reset value: 0x0 Gives the raw
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// interrupt state (before masking)
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// of SSIRXINTR
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#define SSI_RIS_RXRIS_M 0x00000004
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#define SSI_RIS_RXRIS_S 2
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#define SSI_RIS_RTRIS 0x00000002 // SSI SSIRTINTR raw state (RO)
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// Reset value: 0x0 Gives the raw
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// interrupt state (before masking)
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// of SSIRTINTR
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#define SSI_RIS_RTRIS_M 0x00000002
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#define SSI_RIS_RTRIS_S 1
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#define SSI_RIS_RORRIS 0x00000001 // SSI SSIRORINTR raw state (RO)
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// Reset value: 0x0 Gives the raw
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// interrupt state (before masking)
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// of SSIRORINTR
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#define SSI_RIS_RORRIS_M 0x00000001
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#define SSI_RIS_RORRIS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_MIS register.
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//
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//*****************************************************************************
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#define SSI_MIS_TXMIS 0x00000008 // SSI SSITXINTR masked state (RO)
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// Reset value: 0x0 Gives the
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// interrupt state (after masking)
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// of SSITXINTR
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#define SSI_MIS_TXMIS_M 0x00000008
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#define SSI_MIS_TXMIS_S 3
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#define SSI_MIS_RXMIS 0x00000004 // SSI SSIRXINTR masked state (RO)
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// Reset value: 0x0 Gives the
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// interrupt state (after masking)
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// of SSIRXINTR
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#define SSI_MIS_RXMIS_M 0x00000004
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#define SSI_MIS_RXMIS_S 2
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#define SSI_MIS_RTMIS 0x00000002 // SSI SSIRTINTR masked state (RO)
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// Reset value: 0x0 Gives the
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// interrupt state (after masking)
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// of SSIRTINTR
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#define SSI_MIS_RTMIS_M 0x00000002
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#define SSI_MIS_RTMIS_S 1
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#define SSI_MIS_RORMIS 0x00000001 // SSI SSIRORINTR masked state
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// (RO) Reset value: 0x0 Gives the
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// interrupt state (after masking)
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// of SSIRORINTR
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#define SSI_MIS_RORMIS_M 0x00000001
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#define SSI_MIS_RORMIS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_ICR register.
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//
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//*****************************************************************************
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#define SSI_ICR_RTIC 0x00000002 // SSI receive time-out interrupt
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// clear (W1C) Reset value: 0x0 0:
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// No effect on interrupt 1: Clears
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// interrupt
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#define SSI_ICR_RTIC_M 0x00000002
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#define SSI_ICR_RTIC_S 1
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#define SSI_ICR_RORIC 0x00000001 // SSI receive overrun interrupt
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// clear (W1C) Reset value: 0x0 0:
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// No effect on interrupt 1: Clears
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// interrupt
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#define SSI_ICR_RORIC_M 0x00000001
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#define SSI_ICR_RORIC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_DMACTL register.
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//
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//*****************************************************************************
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#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA enable 0: uDMA for
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// the transmit FIFO is disabled.
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// 1: uDMA for the transmit FIFO is
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// enabled.
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#define SSI_DMACTL_TXDMAE_M 0x00000002
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#define SSI_DMACTL_TXDMAE_S 1
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#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA enable 0: uDMA for
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// the receive FIFO is disabled. 1:
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// uDMA for the receive FIFO is
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// enabled.
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#define SSI_DMACTL_RXDMAE_M 0x00000001
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#define SSI_DMACTL_RXDMAE_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_CC register.
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//
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//*****************************************************************************
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#define SSI_CC_CS_M 0x00000007 // SSI baud and system clock
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// source The following bits
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// determine the clock source that
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// generates the baud and system
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// clocks for the SSI. bit0
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// (PIOSC): 1: The SSI baud clock
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// is determined by the IO DIV
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// setting in the system
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// controller. 0: The SSI baud
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// clock is determined by the SYS
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// DIV setting in the system
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// controller. bit1: Unused bit2:
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// (DSEN) Only meaningful when the
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// system is in deep sleep mode.
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// This bit is a don't care when
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// not in sleep mode. 1: The SSI
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// system clock is running on the
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// same clock as the baud clock, as
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// per PIOSC setting above. 0: The
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// SSI system clock is determined
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// by the SYS DIV setting in the
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// system controller.
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#define SSI_CC_CS_S 0
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#endif // __HW_SSI_H__
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