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df37e69b90
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
286 lines
17 KiB
C
Executable File
286 lines
17 KiB
C
Executable File
/******************************************************************************
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* Filename: hw_i2cs.h
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* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
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* Revision: $Revision: 9943 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_I2CS_H__
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#define __HW_I2CS_H__
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//*****************************************************************************
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//
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// The following are defines for the I2CS register offsets.
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//
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//*****************************************************************************
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#define I2CS_OAR 0x40020800 // I2C slave own address This
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// register consists of seven
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// address bits that identify the
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// CC2538 I2C device on the I2C
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// bus.
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#define I2CS_STAT 0x40020804 // I2C slave control and status
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// This register functions as a
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// control register when written,
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// and a status register when read.
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#define I2CS_CTRL 0x40020804 // I2C slave control and status
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// This register functions as a
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// control register when written,
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// and a status register when read.
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#define I2CS_DR 0x40020808 // I2C slave data This register
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// contains the data to be
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// transmitted when in the slave
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// transmit state, and the data
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// received when in the slave
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// receive state.
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#define I2CS_IMR 0x4002080C // I2C slave interrupt mask This
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// register controls whether a raw
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// interrupt is promoted to a
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// controller interrupt.
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#define I2CS_RIS 0x40020810 // I2C slave raw interrupt status
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// This register specifies whether
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// an interrupt is pending.
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#define I2CS_MIS 0x40020814 // I2C slave masked interrupt
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// status This register specifies
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// whether an interrupt was
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// signaled.
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#define I2CS_ICR 0x40020818 // I2C slave interrupt clear This
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// register clears the raw
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// interrupt. A read of this
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// register returns no meaningful
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// data.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CS_OAR register.
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//
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//*****************************************************************************
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#define I2CS_OAR_OAR_M 0x0000007F // I2C slave own address This
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// field specifies bits A6 through
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// A0 of the slave address.
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#define I2CS_OAR_OAR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CS_STAT register.
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//
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//*****************************************************************************
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#define I2CS_STAT_FBR 0x00000004 // First byte received 1: The
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// first byte following the slave's
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// own address has been received.
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// 0: The first byte has not been
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// received. This bit is only valid
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// when the RREQ bit is set and is
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// automatically cleared when data
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// has been read from the I2CSDR
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// register. Note: This bit is not
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// used for slave transmit
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// operations.
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#define I2CS_STAT_FBR_M 0x00000004
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#define I2CS_STAT_FBR_S 2
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#define I2CS_STAT_TREQ 0x00000002 // Transmit request 1: The I2C
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// controller has been addressed as
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// a slave transmitter and is using
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// clock stretching to delay the
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// master until data has been
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// written to the I2CSDR register.
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// 0: No outstanding transmit
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// request.
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#define I2CS_STAT_TREQ_M 0x00000002
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#define I2CS_STAT_TREQ_S 1
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#define I2CS_STAT_RREQ 0x00000001 // Receive request 1: The I2C
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// controller has outstanding
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// receive data from the I2C master
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// and is using clock stretching to
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// delay the master until data has
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// been read from the I2CSDR
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// register. 0: No outstanding
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// receive data
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#define I2CS_STAT_RREQ_M 0x00000001
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#define I2CS_STAT_RREQ_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CS_CTRL register.
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//
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//*****************************************************************************
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#define I2CS_CTRL_DA 0x00000001 // Device active 0: Disables the
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// I2C slave operation 1: Enables
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// the I2C slave operation
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#define I2CS_CTRL_DA_M 0x00000001
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#define I2CS_CTRL_DA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CS_DR register.
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//
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//*****************************************************************************
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#define I2CS_DR_DATA_M 0x000000FF // Data for transfer This field
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// contains the data for transfer
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// during a slave receive or
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// transmit operation.
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#define I2CS_DR_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CS_IMR register.
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//
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//*****************************************************************************
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#define I2CS_IMR_STOPIM 0x00000004 // Stop condition interrupt mask
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// 1: The STOP condition interrupt
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// is sent to the interrupt
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// controller when the STOPRIS bit
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// in the I2CSRIS register is set.
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// 0: The STOPRIS interrupt is
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// supressed and not sent to the
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// interrupt controller.
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#define I2CS_IMR_STOPIM_M 0x00000004
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#define I2CS_IMR_STOPIM_S 2
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#define I2CS_IMR_STARTIM 0x00000002 // Start condition interrupt mask
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// 1: The START condition interrupt
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// is sent to the interrupt
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// controller when the STARTRIS bit
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// in the I2CSRIS register is set.
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// 0: The STARTRIS interrupt is
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// supressed and not sent to the
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// interrupt controller.
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#define I2CS_IMR_STARTIM_M 0x00000002
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#define I2CS_IMR_STARTIM_S 1
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#define I2CS_IMR_DATAIM 0x00000001 // Data interrupt mask 1: The data
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// received or data requested
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// interrupt is sent to the
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// interrupt controller when the
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// DATARIS bit in the I2CSRIS
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// register is set. 0: The DATARIS
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// interrupt is surpressed and not
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// sent to the interrupt
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// controller.
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#define I2CS_IMR_DATAIM_M 0x00000001
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#define I2CS_IMR_DATAIM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CS_RIS register.
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//
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//*****************************************************************************
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#define I2CS_RIS_STOPRIS 0x00000004 // Stop condition raw interrupt
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// status 1: A STOP condition
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// interrupt is pending. 0: No
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// interrupt This bit is cleared by
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// writing 1 to the STOPIC bit in
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// the I2CSICR register.
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#define I2CS_RIS_STOPRIS_M 0x00000004
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#define I2CS_RIS_STOPRIS_S 2
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#define I2CS_RIS_STARTRIS 0x00000002 // Start condition raw interrupt
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// status 1: A START condition
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// interrupt is pending. 0: No
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// interrupt This bit is cleared by
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// writing 1 to the STARTIC bit in
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// the I2CSICR register.
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#define I2CS_RIS_STARTRIS_M 0x00000002
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#define I2CS_RIS_STARTRIS_S 1
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#define I2CS_RIS_DATARIS 0x00000001 // Data raw interrupt status 1: A
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// data received or data requested
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// interrupt is pending. 0: No
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// interrupt This bit is cleared by
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// writing 1 to the DATAIC bit in
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// the I2CSICR register.
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#define I2CS_RIS_DATARIS_M 0x00000001
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#define I2CS_RIS_DATARIS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CS_MIS register.
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//
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//*****************************************************************************
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#define I2CS_MIS_STOPMIS 0x00000004 // Stop condition masked interrupt
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// status 1: An unmasked STOP
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// condition interrupt is pending.
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// 0: An interrupt has not occurred
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// or is masked. This bit is
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// cleared by writing 1 to the
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// STOPIC bit in the I2CSICR
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// register.
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#define I2CS_MIS_STOPMIS_M 0x00000004
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#define I2CS_MIS_STOPMIS_S 2
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#define I2CS_MIS_STARTMIS 0x00000002 // Start condition masked
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// interrupt status 1: An unmasked
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// START condition interrupt is
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// pending. 0: An interrupt has not
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// occurred or is masked. This bit
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// is cleared by writing 1 to the
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// STARTIC bit in the I2CSICR
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// register.
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#define I2CS_MIS_STARTMIS_M 0x00000002
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#define I2CS_MIS_STARTMIS_S 1
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#define I2CS_MIS_DATAMIS 0x00000001 // Data masked interrupt status 1:
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// An unmasked data received or
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// data requested interrupt is
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// pending. 0: An interrupt has not
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// occurred or is masked. This bit
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// is cleared by writing 1 to the
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// DATAIC bit in the I2CSICR
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// register.
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#define I2CS_MIS_DATAMIS_M 0x00000001
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#define I2CS_MIS_DATAMIS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CS_ICR register.
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//
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//*****************************************************************************
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#define I2CS_ICR_STOPIC 0x00000004 // Stop condition interrupt clear
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// Writing 1 to this bit clears the
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// STOPRIS bit in the I2CSRIS
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// register and the STOPMIS bit in
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// the I2CSMIS register. A read of
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// this register returns no
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// meaningful data.
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#define I2CS_ICR_STOPIC_M 0x00000004
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#define I2CS_ICR_STOPIC_S 2
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#define I2CS_ICR_STARTIC 0x00000002 // Start condition interrupt vlear
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// Writing 1 to this bit clears the
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// STARTRIS bit in the I2CSRIS
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// register and the STARTMIS bit in
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// the I2CSMIS register. A read of
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// this register returns no
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// meaningful data.
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#define I2CS_ICR_STARTIC_M 0x00000002
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#define I2CS_ICR_STARTIC_S 1
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#define I2CS_ICR_DATAIC 0x00000001 // Data interrupt clear Writing 1
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// to this bit clears the DATARIS
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// bit in the I2CSRIS register and
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// the DATAMIS bit in the I2CSMIS
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// register. A read of this
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// register returns no meaningful
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// data.
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#define I2CS_ICR_DATAIC_M 0x00000001
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#define I2CS_ICR_DATAIC_S 0
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#endif // __HW_I2CS_H__
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