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df37e69b90
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
1032 lines
66 KiB
C
Executable File
1032 lines
66 KiB
C
Executable File
/******************************************************************************
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* Filename: hw_gptimer.h
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* Revised: $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
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* Revision: $Revision: 9735 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_GPTIMER_H__
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#define __HW_GPTIMER_H__
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//*****************************************************************************
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//
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// The following are defines for the GPTIMER register offsets.
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//
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//*****************************************************************************
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#define GPTIMER_O_CFG 0x00000000 // GPTM configuration This
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// register configures the global
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// operation of the GPTM. The value
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// written to this register
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// determines whether the GPTM is
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// in 32-bit mode (concatenated
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// timers) or in 16-bit mode
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// (individual, split timers).
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#define GPTIMER_O_TAMR 0x00000004 // GPTM Timer A mode This register
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// configures the GPTM based on the
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// configuration selected in the
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// CFG register. This register
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// controls the modes for Timer A
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// when it is used individually.
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// When Timer A and Timer B are
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// concatenated, this register
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// controls the modes for both
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// Timer A and Timer B, and the
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// contents of TBMR are ignored.
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#define GPTIMER_O_TBMR 0x00000008 // GPTM Timer B mode This register
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// configures the GPTM based on the
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// configuration selected in the
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// CFG register. This register
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// controls the modes for Timer B
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// when it is used individually.
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// When Timer A and Timer B are
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// concatenated, this register is
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// ignored and TBMR controls the
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// modes for both Timer A and Timer
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// B.
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#define GPTIMER_O_CTL 0x0000000C // GPTM control This register is
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// used alongside the CFG and TnMR
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// registers to fine-tune the timer
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// configuration, and to enable
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// other features such as timer
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// stall.
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#define GPTIMER_O_SYNC 0x00000010 // GPTM synchronize Note: This
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// register is implemented on GPTM
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// 0 base address only. This
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// register does however, allow
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// software to synchronize a number
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// of timers.
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#define GPTIMER_O_IMR 0x00000018 // GPTM interrupt mask This
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// register allows software to
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// enable and disable GPTM
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// controller-level interrupts.
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// Setting a bit enables the
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// corresponding interrupt, while
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// clearing a bit disables it.
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#define GPTIMER_O_RIS 0x0000001C // GPTM raw interrupt status This
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// register shows the state of the
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// GPTM internal interrupt signal.
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// These bits are set whether or
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// not the interrupt is masked in
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// the IMR register. Each bit can
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// be cleared by writing 1 to its
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// corresponding bit in ICR.
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#define GPTIMER_O_MIS 0x00000020 // GPTM masked interrupt status
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// This register shows the state of
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// the GPTM controller-level
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// interrupt. If an interrupt is
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// unmasked in IMR, and there is an
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// event that causes the interrupt
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// to be asserted, the
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// corresponding bit is set in this
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// register. All bits are cleared
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// by writing 1 to the
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// corresponding bit in ICR.
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#define GPTIMER_O_ICR 0x00000024 // GPTM interrupt clear This
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// register is used to clear the
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// status bits in the RIS and MIS
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// registers. Writing 1 to a bit
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// clears the corresponding bit in
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// the RIS and MIS registers.
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#define GPTIMER_O_TAILR 0x00000028 // GPTM Timer A interval load When
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// the Timer is counting down, this
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// register is used to load the
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// starting count value into the
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// Timer. When the Timer is
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// counting up, this register sets
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// the upper bound for the timeout
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// event. When a GPTM is configured
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// to one of the 32-bit modes,
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// TAILR appears as a 32-bit
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// register (the upper 16-bits
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// correspond to the contents of
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// the GPTM Timer B Interval Load
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// (TBILR) register). In a 16-bit
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// mode, the upper 16 bits of this
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// register read as 0s and have no
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// effect on the state of TBILR.
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#define GPTIMER_O_TBILR 0x0000002C // GPTM Timer B interval load When
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// the Timer is counting down, this
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// register is used to load the
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// starting count value into the
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// Timer. When the Timer is
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// counting up, this register sets
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// the upper bound for the time-out
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// event. When a GPTM is configured
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// to one of the 32-bit modes, the
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// contents of bits [15:0] in this
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// register are loaded into the
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// upper 16 bits of the TAILR
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// register. Reads from this
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// register return the current
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// value of Timer B and writes are
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// ignored. In a 16-bit mode, bits
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// [15:0] are used for the load
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// value. Bits [31:16] are reserved
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// in both cases.
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#define GPTIMER_O_TAMATCHR 0x00000030 // GPTM Timer A match This
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// register is loaded with a match
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// value. Interrupts can be
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// generated when the Timer value
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// is equal to the value in this
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// register in one-shot or periodic
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// mode. When a GPTM is configured
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// to one of the 32-bit modes,
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// TAMATCHR appears as a 32-bit
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// register (the upper 16-bits
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// correspond to the contents of
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// the GPTM Timer B match
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// (GPTMTBMATCHR) register). In a
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// 16-bit mode, the upper 16 bits
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// of this register read as 0s and
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// have no effect on the state of
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// TBMATCHR.
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#define GPTIMER_O_TBMATCHR 0x00000034 // PTM Timer B match This register
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// is loaded with a match value.
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// Interrupts can be generated when
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// the Timer value is equal to the
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// value in this register in
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// one-shot or periodic mode. When
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// a GPTM is configured to one of
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// the 32-bit modes, the contents
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// of bits [15:0] in this register
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// are loaded into the upper 16
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// bits of the TAMATCHR register.
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// Reads from this register return
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// the current match value of Timer
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// B and writes are ignored. In a
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// 16-bit mode, bits [15:0] are
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// used for the match value. Bits
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// [31:16] are reserved in both
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// cases.
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#define GPTIMER_O_TAPR 0x00000038 // GPTM Timer A prescale This
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// register allows software to
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// extend the range of the 16-bit
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// Timers in periodic and one-shot
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// modes.
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#define GPTIMER_O_TBPR 0x0000003C // GPTM Timer B prescale This
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// register allows software to
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// extend the range of the 16-bit
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// Timers in periodic and one-shot
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// modes.
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#define GPTIMER_O_TAPMR 0x00000040 // GPTM Timer A prescale match
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// This register effectively
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// extends the range of TAMATCHR to
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// 24 bits when operating in
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// 16-bit, one-shot or periodic
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// mode.
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#define GPTIMER_O_TBPMR 0x00000044 // GPTM Timer B prescale match
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// This register effectively
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// extends the range ofMTBMATCHR to
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// 24 bits when operating in
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// 16-bit, one-shot or periodic
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// mode.
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#define GPTIMER_O_TAR 0x00000048 // GPTM Timer A This register
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// shows the current value of the
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// Timer A counter. When a GPTM is
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// configured to one of the 32-bit
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// modes, TAR appears as a 32-bit
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// register (the upper 16-bits
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// correspond to the contents of
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// the GPTM Timer B (TBR)
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// register). In the16-bit Input
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// edge count, input edge time, and
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// PWM modes, bits [15:0] contain
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// the value of the counter and
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// bits 23:16 contain the value of
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// the prescaler, which is the
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// upper 8 bits of the count. Bits
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// [31:24] always read as 0. To
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// read the value of the prescaler
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// in 16-bit, one-shot and periodic
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// modes, read bits [23:16] in the
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// TAV register.
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#define GPTIMER_O_TBR 0x0000004C // GPTM Timer B This register
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// shows the current value of the
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// Timer B counter. When a GPTM is
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// configured to one of the 32-bit
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// modes, the contents of bits
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// [15:0] in this register are
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// loaded into the upper 16 bits of
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// the TAR register. Reads from
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// this register return the current
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// value of Timer B. In a 16-bit
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// mode, bits 15:0 contain the
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// value of the counter and bits
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// [23:16] contain the value of the
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// prescaler in Input edge count,
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// input edge time, and PWM modes,
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// which is the upper 8 bits of the
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// count. Bits [31:24] always read
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// as 0. To read the value of the
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// prescaler in 16-bit, one-shot
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// and periodic modes, read bits
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// [23:16] in the TBV register.
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#define GPTIMER_O_TAV 0x00000050 // GPTM Timer A value When read,
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// this register shows the current,
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// free-running value of Timer A in
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// all modes. Software can use this
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// value to determine the time
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// elapsed between an interrupt and
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// the ISR entry when using the
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// snapshot feature with the
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// periodic operating mode. When
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// written, the value written into
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// this register is loaded into the
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// TAR register on the next clock
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// cycle. When a GPTM is configured
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// to one of the 32-bit modes, TAV
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// appears as a 32-bit register
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// (the upper 16-bits correspond to
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// the contents of the GPTM Timer B
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// Value (TBV) register). In a
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// 16-bit mode, bits [15:0] contain
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// the value of the counter and
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// bits [23:16] contain the
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// current, free-running value of
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// the prescaler, which is the
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// upper 8 bits of the count in
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// input edge count, input edge
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// time, PWM and one-shot or
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// periodic up count modes. In
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// one-shot or periodic down count
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// modes, the prescaler stored in
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// [23:16] is a true prescaler,
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// meaning bits [23:16] count down
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// before decrementing the value in
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// bits [15:0]. The prescaler its
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// [31:24] always read as 0.
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#define GPTIMER_O_TBV 0x00000054 // GPTM Timer B value When read,
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// this register shows the current,
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// free-running value of Timer B in
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// all modes. Software can use this
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// value to determine the time
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// elapsed between an interrupt and
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// the ISR entry. When written, the
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// value written into this register
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// is loaded into the TBR register
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// on the next clock cycle. When a
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// GPTM is configured to one of the
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// 32-bit modes, the contents of
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// bits 15:0 in this register are
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// loaded into the upper 16 bits of
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// the TAV register. Reads from
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// this register return the current
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// free-running value of Timer B.
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// In a 16-bit mode, bits [15:0]
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// contain the value of the counter
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// and bits [23:16] contain the
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// current, free-running value of
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// the prescaler, which is the
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// upper 8 bits of the count in
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// input edge count, input edge
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// time, PWM and one-shot or
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// periodic up count modes. In
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// one-shot or periodic down count
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// modes, the prescaler stored in
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// [23:16] is a true prescaler,
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// meaning bits [23:16] count down
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// before decrementing the value in
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// bits [15:0]. The prescaler its
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// [31:24] always read as 0.
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#define GPTIMER_O_TAPS 0x0000005C // GPTM Timer A prescale snapshot
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// For the 32-bit wide GPTM, this
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// register shows the current value
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// of the Timer A prescaler in the
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// 32-bit modes. This register is
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// ununsed in 16-bit GPTM mode.
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#define GPTIMER_O_TBPS 0x00000060 // GPTM Timer B prescale snapshot
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// For the 32-bit wide GPTM, this
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// register shows the current value
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// of the Timer B prescaler in the
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// 32-bit modes. This register is
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// ununsed in 16-bit GPTM mode.
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#define GPTIMER_O_TAPV 0x00000064 // GPTM Timer A prescale value For
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// the 32-bit wide GPTM, this
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// register shows the current
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// free-running value of the Timer
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// A prescaler in the 32-bit modes.
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// Software can use this value in
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// conjunction with the TAV
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// register to determine the time
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// elapsed between an interrupt and
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// the ISR entry. This register is
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// ununsed in 16- or 32-bit GPTM
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// mode.
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#define GPTIMER_O_TBPV 0x00000068 // GPTM Timer B prescale value For
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// the 32-bit wide GPTM, this
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// register shows the current
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// free-running value of the Timer
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// B prescaler in the 32-bit modes.
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// Software can use this value in
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// conjunction with the TBV
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// register to determine the time
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// elapsed between an interrupt and
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// the ISR entry. This register is
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// ununsed in 16- or 32-bit GPTM
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// mode.
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#define GPTIMER_O_PP 0x00000FC0 // GPTM peripheral properties The
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// PP register provides information
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// regarding the properties of the
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// general-purpose Timer module.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_CFG register.
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//
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//*****************************************************************************
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#define GPTIMER_CFG_GPTMCFG_M 0x00000007 // GPTM configuration The GPTMCFG
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// values are defined as follows:
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// 0x0: 32-bit timer configuration.
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// 0x1: 32-bit real-time clock 0x2:
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// Reserved 0x3: Reserved 0x4:
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// 16-bit timer configuration. The
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// function is controlled by bits
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// [1:0] of GPTMTAMR and GPTMTBMR.
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// 0x5-0x7: Reserved
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#define GPTIMER_CFG_GPTMCFG_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TAMR register.
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//
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//*****************************************************************************
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#define GPTIMER_TAMR_TAPLO 0x00000800 // Legacy PWM operation 0: Legacy
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// operation 1: CCP is set to 1 on
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// time-out.
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#define GPTIMER_TAMR_TAPLO_M 0x00000800
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#define GPTIMER_TAMR_TAPLO_S 11
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#define GPTIMER_TAMR_TAMRSU 0x00000400 // Timer A match register update
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// mode 0: Update GPTMAMATCHR and
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// GPTMAPR if used on the next
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// cycle. 1: Update GPTMAMATCHR and
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// GPTMAPR if used on the next
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// time-out. If the timer is
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// disabled (TAEN is clear) when
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// this bit is set, GPTMTAMATCHR
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// and GPTMTAPR are updated when
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// the timer is enabled. If the
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// timer is stalled (TASTALL is
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// set), GPTMTAMATCHR and GPTMTAPR
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// are updated according to the
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// configuration of this bit.
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#define GPTIMER_TAMR_TAMRSU_M 0x00000400
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#define GPTIMER_TAMR_TAMRSU_S 10
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#define GPTIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM interrupt
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// enable This bit enables
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// interrupts in PWM mode on
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// rising, falling, or both edges
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// of the CCP output. 0: Interrupt
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// is disabled. 1: Interrupt is
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// enabled. This bit is valid only
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// in PWM mode.
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#define GPTIMER_TAMR_TAPWMIE_M 0x00000200
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#define GPTIMER_TAMR_TAPWMIE_S 9
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#define GPTIMER_TAMR_TAILD 0x00000100 // GPTM Timer A PWM interval load
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// write 0: Update the GPTMTAR
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// register with the value in the
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// GPTMTAILR register on the next
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// cycle. If the prescaler is used,
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// update the GPTMTAPS register
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// with the value in the GPTMTAPR
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// register on the next cycle. 1:
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// Update the GPTMTAR register with
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// the value in the GPTMTAILR
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// register on the next cycle. If
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// the prescaler is used, update
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// the GPTMTAPS register with the
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// value in the GPTMTAPR register
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// on the next time-out.
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#define GPTIMER_TAMR_TAILD_M 0x00000100
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#define GPTIMER_TAMR_TAILD_S 8
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#define GPTIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A snap-shot mode 0:
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// Snap-shot mode is disabled. 1:
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// If Timer A is configured in
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// periodic mode, the actual
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// free-running value of Timer A is
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// loaded at the time-out event
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// into the GPTM Timer A (GPTMTAR)
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// register.
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#define GPTIMER_TAMR_TASNAPS_M 0x00000080
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#define GPTIMER_TAMR_TASNAPS_S 7
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#define GPTIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A wait-on-trigger 0:
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// Timer A begins counting as soon
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// as it is enabled. 1: If Timer A
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// is enabled (TAEN is set in the
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// GPTMCTL register), Timer A does
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// not begin counting until it
|
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// receives a trigger from the
|
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// Timer in the previous position
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// in the daisy-chain. This bit
|
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// must be clear for GP Timer
|
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// module 0, Timer A.
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|
#define GPTIMER_TAMR_TAWOT_M 0x00000040
|
|
#define GPTIMER_TAMR_TAWOT_S 6
|
|
#define GPTIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A match interrupt
|
|
// enable 0: The match interrupt is
|
|
// disabled. 1: An interrupt is
|
|
// generated when the match value
|
|
// in the GPTMTAMATCHR register is
|
|
// reached in the one-shot and
|
|
// periodic modes.
|
|
#define GPTIMER_TAMR_TAMIE_M 0x00000020
|
|
#define GPTIMER_TAMR_TAMIE_S 5
|
|
#define GPTIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A count direction 0:
|
|
// The timer counts down. 1: The
|
|
// timer counts up. When counting
|
|
// up, the timer starts from a
|
|
// value of 0x0.
|
|
#define GPTIMER_TAMR_TACDIR_M 0x00000010
|
|
#define GPTIMER_TAMR_TACDIR_S 4
|
|
#define GPTIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A alternate mode 0:
|
|
// Capture mode is enabled. 1: PWM
|
|
// mode is enabled. Note: To enable
|
|
// PWM mode, the TACM bit must be
|
|
// cleared and the TAMR field must
|
|
// be configured to 0x2.
|
|
#define GPTIMER_TAMR_TAAMS_M 0x00000008
|
|
#define GPTIMER_TAMR_TAAMS_S 3
|
|
#define GPTIMER_TAMR_TACMR 0x00000004 // GPTM Timer A capture mode 0:
|
|
// Edge-count mode 1: Edge-time
|
|
// mode
|
|
#define GPTIMER_TAMR_TACMR_M 0x00000004
|
|
#define GPTIMER_TAMR_TACMR_S 2
|
|
#define GPTIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A mode 0x0: Reserved
|
|
// 0x1: One-shot mode 0x2: Periodic
|
|
// mode 0x3: Capture mode The timer
|
|
// mode is based on the timer
|
|
// configuration defined by bits
|
|
// [2:0] in the GPTMCFG register.
|
|
#define GPTIMER_TAMR_TAMR_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPTIMER_O_TBMR register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPTIMER_TBMR_TBPLO 0x00000800 // Legacy PWM operation 0: Legacy
|
|
// operation 1: CCP is set to 1 on
|
|
// time-out.
|
|
#define GPTIMER_TBMR_TBPLO_M 0x00000800
|
|
#define GPTIMER_TBMR_TBPLO_S 11
|
|
#define GPTIMER_TBMR_TBMRSU 0x00000400 // Timer B match register update
|
|
// mode 0: Update the GPTMBMATCHR
|
|
// and the GPTMBPR, if used on the
|
|
// next cycle. 1: Update the
|
|
// GPTMBMATCHR and the GPTMBPR, if
|
|
// used on the next time-out. If
|
|
// the timer is disabled (TAEN is
|
|
// clear) when this bit is set,
|
|
// GPTMTBMATCHR and GPTMTBPR are
|
|
// updated when the timer is
|
|
// enabled. If the timer is stalled
|
|
// (TBSTALL is set), GPTMTBMATCHR
|
|
// and GPTMTBPR are updated
|
|
// according to the configuration
|
|
// of this bit.
|
|
#define GPTIMER_TBMR_TBMRSU_M 0x00000400
|
|
#define GPTIMER_TBMR_TBMRSU_S 10
|
|
#define GPTIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM interrupt
|
|
// enable This bit enables
|
|
// interrupts in PWM mode on
|
|
// rising, falling, or both edges
|
|
// of the CCP output. 0: Interrupt
|
|
// is disabled. 1: Interrupt is
|
|
// enabled. This bit is valid only
|
|
// in PWM mode.
|
|
#define GPTIMER_TBMR_TBPWMIE_M 0x00000200
|
|
#define GPTIMER_TBMR_TBPWMIE_S 9
|
|
#define GPTIMER_TBMR_TBILD 0x00000100 // GPTM Timer B PWM interval load
|
|
// write 0: Update the GPTMTBR
|
|
// register with the value in the
|
|
// GPTMTBILR register on the next
|
|
// cycle. If the prescaler is used,
|
|
// update the GPTMTBPS register
|
|
// with the value in the GPTMTBPR
|
|
// register on the next cycle. 1:
|
|
// Update the GPTMTBR register with
|
|
// the value in the GPTMTBILR
|
|
// register on the next cycle. If
|
|
// the prescaler is used, update
|
|
// the GPTMTBPS register with the
|
|
// value in the GPTMTBPR register
|
|
// on the next time-out.
|
|
#define GPTIMER_TBMR_TBILD_M 0x00000100
|
|
#define GPTIMER_TBMR_TBILD_S 8
|
|
#define GPTIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B snap-shot mode 0:
|
|
// Snap-shot mode is disabled. 1:
|
|
// If Timer B is configured in the
|
|
// periodic mode, the actual
|
|
// free-running value of Timer A is
|
|
// loaded into the GPTM Timer B
|
|
// (GPTMTBR) register at the
|
|
// time-out event.
|
|
#define GPTIMER_TBMR_TBSNAPS_M 0x00000080
|
|
#define GPTIMER_TBMR_TBSNAPS_S 7
|
|
#define GPTIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B wait-on-trigger 0:
|
|
// Timer B begins counting as soon
|
|
// as it is enabled. 1: If Timer B
|
|
// is enabled (TBEN is set in the
|
|
// GPTMCTL register), Timer B does
|
|
// not begin counting until it
|
|
// receives a trigger from the
|
|
// timer in the previous position
|
|
// in the daisy-chain.
|
|
#define GPTIMER_TBMR_TBWOT_M 0x00000040
|
|
#define GPTIMER_TBMR_TBWOT_S 6
|
|
#define GPTIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B match interrupt
|
|
// enable 0: The match interrupt is
|
|
// disabled. 1: An interrupt is
|
|
// generated when the match value
|
|
// in the GPTMTBMATCHR register is
|
|
// reached in the one-shot and
|
|
// periodic modes.
|
|
#define GPTIMER_TBMR_TBMIE_M 0x00000020
|
|
#define GPTIMER_TBMR_TBMIE_S 5
|
|
#define GPTIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B count direction 0:
|
|
// The timer counts down. 1: The
|
|
// timer counts up. When counting
|
|
// up, the timer starts from a
|
|
// value of 0x0.
|
|
#define GPTIMER_TBMR_TBCDIR_M 0x00000010
|
|
#define GPTIMER_TBMR_TBCDIR_S 4
|
|
#define GPTIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B alternate mode 0:
|
|
// Capture mode is enabled. 1: PWM
|
|
// mode is enabled. Note: To enable
|
|
// PWM mode, the TBCM bit must be
|
|
// cleared and the TBMR field must
|
|
// be configured to 0x2.
|
|
#define GPTIMER_TBMR_TBAMS_M 0x00000008
|
|
#define GPTIMER_TBMR_TBAMS_S 3
|
|
#define GPTIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B capture mode 0:
|
|
// Edge-count mode 1: Edge-time
|
|
// mode
|
|
#define GPTIMER_TBMR_TBCMR_M 0x00000004
|
|
#define GPTIMER_TBMR_TBCMR_S 2
|
|
#define GPTIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B mode 0x0: Reserved
|
|
// 0x1: One-shot timer mode 0x2:
|
|
// Periodic timer mode 0x3: Capture
|
|
// mode The timer mode is based on
|
|
// the timer configuration defined
|
|
// by bits [2:0] in the GPTMCFG
|
|
// register.
|
|
#define GPTIMER_TBMR_TBMR_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPTIMER_O_CTL register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPTIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM output level
|
|
// 0: Output is unaffected. 1:
|
|
// Output is inverted.
|
|
#define GPTIMER_CTL_TBPWML_M 0x00004000
|
|
#define GPTIMER_CTL_TBPWML_S 14
|
|
#define GPTIMER_CTL_TBOTE 0x00002000 // GPTM Timer B output trigger
|
|
// enable 0: The ADC trigger of
|
|
// output Timer B is disabled. 1:
|
|
// The ADC trigger of output Timer
|
|
// B is enabled.
|
|
#define GPTIMER_CTL_TBOTE_M 0x00002000
|
|
#define GPTIMER_CTL_TBOTE_S 13
|
|
#define GPTIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B event mode 0x0:
|
|
// Positive edge 0x1: Negative edge
|
|
// 0x2: Reserved 0x3: Both edges
|
|
#define GPTIMER_CTL_TBEVENT_S 10
|
|
#define GPTIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B stall enable 0:
|
|
// Timer B continues counting while
|
|
// the processor is halted by the
|
|
// debugger. 1: Timer B freezes
|
|
// counting while the processor is
|
|
// halted by the debugger.
|
|
#define GPTIMER_CTL_TBSTALL_M 0x00000200
|
|
#define GPTIMER_CTL_TBSTALL_S 9
|
|
#define GPTIMER_CTL_TBEN 0x00000100 // GPTM Timer B enable 0: Timer B
|
|
// is disabled. 1: Timer B is
|
|
// enabled and begins counting or
|
|
// the capture logic is enabled
|
|
// based on the GPTMCFG register.
|
|
#define GPTIMER_CTL_TBEN_M 0x00000100
|
|
#define GPTIMER_CTL_TBEN_S 8
|
|
#define GPTIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM output level
|
|
// 0: Output is unaffected. 1:
|
|
// Output is inverted.
|
|
#define GPTIMER_CTL_TAPWML_M 0x00000040
|
|
#define GPTIMER_CTL_TAPWML_S 6
|
|
#define GPTIMER_CTL_TAOTE 0x00000020 // GPTM Timer A output trigger
|
|
// enable 0: The ADC trigger of
|
|
// output Timer A is disabled. 1:
|
|
// The ADC trigger of output Timer
|
|
// A is enabled.
|
|
#define GPTIMER_CTL_TAOTE_M 0x00000020
|
|
#define GPTIMER_CTL_TAOTE_S 5
|
|
#define GPTIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A event mode 0x0:
|
|
// Positive edge 0x1: Negative edge
|
|
// 0x2: Reserved 0x3: Both edges
|
|
#define GPTIMER_CTL_TAEVENT_S 2
|
|
#define GPTIMER_CTL_TASTALL 0x00000002 // GPTM Timer A stall enable 0:
|
|
// Timer A continues counting while
|
|
// the processor is halted by the
|
|
// debugger. 1: Timer A freezes
|
|
// counting while the processor is
|
|
// halted by the debugger.
|
|
#define GPTIMER_CTL_TASTALL_M 0x00000002
|
|
#define GPTIMER_CTL_TASTALL_S 1
|
|
#define GPTIMER_CTL_TAEN 0x00000001 // GPTM Timer A enable 0: Timer A
|
|
// is disabled. 1: Timer A is
|
|
// enabled and begins counting or
|
|
// the capture logic is enabled
|
|
// based on the GPTMCFG register.
|
|
#define GPTIMER_CTL_TAEN_M 0x00000001
|
|
#define GPTIMER_CTL_TAEN_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPTIMER_O_SYNC register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPTIMER_SYNC_SYNC3_M 0x000000C0 // Synchronize GPTM3 0x0: GPTM3 is
|
|
// not affected. 0x1: A time-out
|
|
// event for Timer A of GPTM3 is
|
|
// triggered. 0x2: A time-out event
|
|
// for Timer B of GPTM3 is
|
|
// triggered. 0x3: A time-out event
|
|
// for Timer A and Timer B of GPTM3
|
|
// is triggered.
|
|
#define GPTIMER_SYNC_SYNC3_S 6
|
|
#define GPTIMER_SYNC_SYNC2_M 0x00000030 // Synchronize GPTM2 0x0: GPTM2 is
|
|
// not affected. 0x1: A time-out
|
|
// event for Timer A of GPTM2 is
|
|
// triggered. 0x2: A time-out event
|
|
// for Timer B of GPTM2 is
|
|
// triggered. 0x3: A time-out event
|
|
// for Timer A and Timer B of GPTM2
|
|
// is triggered.
|
|
#define GPTIMER_SYNC_SYNC2_S 4
|
|
#define GPTIMER_SYNC_SYNC1_M 0x0000000C // Synchronize GPTM1 0x0: GPTM1 is
|
|
// not affected. 0x1: A time-out
|
|
// event for Timer A of GPTM1 is
|
|
// triggered. 0x2: A time-out event
|
|
// for Timer B of GPTM1 is
|
|
// triggered. 0x3: A time-out event
|
|
// for Timer A and Timer B of GPTM1
|
|
// is triggered.
|
|
#define GPTIMER_SYNC_SYNC1_S 2
|
|
#define GPTIMER_SYNC_SYNC0_M 0x00000003 // Synchronize GPTM0 0x0: GPTM0 is
|
|
// not affected. 0x1: A time-out
|
|
// event for Timer A of GPTM0 is
|
|
// triggered. 0x2: A time-out event
|
|
// for Timer B of GPTM0 is
|
|
// triggered. 0x3: A time-out event
|
|
// for Timer A and Timer B of GPTM0
|
|
// is triggered.
|
|
#define GPTIMER_SYNC_SYNC0_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPTIMER_O_IMR register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPTIMER_IMR_TBMIM 0x00000800 // GPTM Timer B match interrupt
|
|
// mask 0: Interrupt is disabled.
|
|
// 1: Interrupt is enabled.
|
|
#define GPTIMER_IMR_TBMIM_M 0x00000800
|
|
#define GPTIMER_IMR_TBMIM_S 11
|
|
#define GPTIMER_IMR_CBEIM 0x00000400 // GPTM Timer B capture event
|
|
// interrupt mask 0: Interrupt is
|
|
// disabled. 1: Interrupt is
|
|
// enabled.
|
|
#define GPTIMER_IMR_CBEIM_M 0x00000400
|
|
#define GPTIMER_IMR_CBEIM_S 10
|
|
#define GPTIMER_IMR_CBMIM 0x00000200 // GPTM Timer B capture match
|
|
// interrupt mask 0: Interrupt is
|
|
// disabled. 1: Interrupt is
|
|
// enabled.
|
|
#define GPTIMER_IMR_CBMIM_M 0x00000200
|
|
#define GPTIMER_IMR_CBMIM_S 9
|
|
#define GPTIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B time-out interrupt
|
|
// mask 0: Interrupt is disabled.
|
|
// 1: Interrupt is enabled.
|
|
#define GPTIMER_IMR_TBTOIM_M 0x00000100
|
|
#define GPTIMER_IMR_TBTOIM_S 8
|
|
#define GPTIMER_IMR_TAMIM 0x00000010 // GPTM Timer A match interrupt
|
|
// mask 0: Interrupt is disabled.
|
|
// 1: Interrupt is enabled.
|
|
#define GPTIMER_IMR_TAMIM_M 0x00000010
|
|
#define GPTIMER_IMR_TAMIM_S 4
|
|
#define GPTIMER_IMR_CAEIM 0x00000004 // GPTM Timer A capture event
|
|
// interrupt mask 0: Interrupt is
|
|
// disabled. 1: Interrupt is
|
|
// enabled.
|
|
#define GPTIMER_IMR_CAEIM_M 0x00000004
|
|
#define GPTIMER_IMR_CAEIM_S 2
|
|
#define GPTIMER_IMR_CAMIM 0x00000002 // GPTM Timer A capture match
|
|
// interrupt mask 0: Interrupt is
|
|
// disabled. 1: Interrupt is
|
|
// enabled.
|
|
#define GPTIMER_IMR_CAMIM_M 0x00000002
|
|
#define GPTIMER_IMR_CAMIM_S 1
|
|
#define GPTIMER_IMR_TATOIM 0x00000001 // GPTM Timer A time-out interrupt
|
|
// mask 0: Interrupt is disabled.
|
|
// 1: Interrupt is enabled.
|
|
#define GPTIMER_IMR_TATOIM_M 0x00000001
|
|
#define GPTIMER_IMR_TATOIM_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPTIMER_O_RIS register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPTIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B match raw
|
|
// interrupt
|
|
#define GPTIMER_RIS_TBMRIS_M 0x00000800
|
|
#define GPTIMER_RIS_TBMRIS_S 11
|
|
#define GPTIMER_RIS_CBERIS 0x00000400 // GPTM Timer B capture event raw
|
|
// interrupt
|
|
#define GPTIMER_RIS_CBERIS_M 0x00000400
|
|
#define GPTIMER_RIS_CBERIS_S 10
|
|
#define GPTIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B capture match raw
|
|
// interrupt
|
|
#define GPTIMER_RIS_CBMRIS_M 0x00000200
|
|
#define GPTIMER_RIS_CBMRIS_S 9
|
|
#define GPTIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B time-out raw
|
|
// interrupt
|
|
#define GPTIMER_RIS_TBTORIS_M 0x00000100
|
|
#define GPTIMER_RIS_TBTORIS_S 8
|
|
#define GPTIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A match raw
|
|
// interrupt
|
|
#define GPTIMER_RIS_TAMRIS_M 0x00000010
|
|
#define GPTIMER_RIS_TAMRIS_S 4
|
|
#define GPTIMER_RIS_CAERIS 0x00000004 // GPTM Timer A capture event raw
|
|
// interrupt
|
|
#define GPTIMER_RIS_CAERIS_M 0x00000004
|
|
#define GPTIMER_RIS_CAERIS_S 2
|
|
#define GPTIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A capture match raw
|
|
// interrupt
|
|
#define GPTIMER_RIS_CAMRIS_M 0x00000002
|
|
#define GPTIMER_RIS_CAMRIS_S 1
|
|
#define GPTIMER_RIS_TATORIS 0x00000001 // GPTM Timer A time-out raw
|
|
// interrupt
|
|
#define GPTIMER_RIS_TATORIS_M 0x00000001
|
|
#define GPTIMER_RIS_TATORIS_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPTIMER_O_MIS register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPTIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B match masked
|
|
// interrupt
|
|
#define GPTIMER_MIS_TBMMIS_M 0x00000800
|
|
#define GPTIMER_MIS_TBMMIS_S 11
|
|
#define GPTIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B capture event
|
|
// masked interrupt
|
|
#define GPTIMER_MIS_CBEMIS_M 0x00000400
|
|
#define GPTIMER_MIS_CBEMIS_S 10
|
|
#define GPTIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B capture match
|
|
// masked interrupt
|
|
#define GPTIMER_MIS_CBMMIS_M 0x00000200
|
|
#define GPTIMER_MIS_CBMMIS_S 9
|
|
#define GPTIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B time-out masked
|
|
// interrupt
|
|
#define GPTIMER_MIS_TBTOMIS_M 0x00000100
|
|
#define GPTIMER_MIS_TBTOMIS_S 8
|
|
#define GPTIMER_MIS_TAMRIS 0x00000010 // GPTM Timer A match raw
|
|
// interrupt
|
|
#define GPTIMER_MIS_TAMRIS_M 0x00000010
|
|
#define GPTIMER_MIS_TAMRIS_S 4
|
|
#define GPTIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A capture event raw
|
|
// interrupt
|
|
#define GPTIMER_MIS_CAEMIS_M 0x00000004
|
|
#define GPTIMER_MIS_CAEMIS_S 2
|
|
#define GPTIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A capture match raw
|
|
// interrupt
|
|
#define GPTIMER_MIS_CAMMIS_M 0x00000002
|
|
#define GPTIMER_MIS_CAMMIS_S 1
|
|
#define GPTIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A time-out raw
|
|
// interrupt
|
|
#define GPTIMER_MIS_TATOMIS_M 0x00000001
|
|
#define GPTIMER_MIS_TATOMIS_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPTIMER_O_ICR register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPTIMER_ICR_WUECINT 0x00010000 // GPTM write update error
|
|
// interrupt clear
|
|
#define GPTIMER_ICR_WUECINT_M 0x00010000
|
|
#define GPTIMER_ICR_WUECINT_S 16
|
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#define GPTIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B match interrupt
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// clear
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#define GPTIMER_ICR_TBMCINT_M 0x00000800
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#define GPTIMER_ICR_TBMCINT_S 11
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#define GPTIMER_ICR_CBECINT 0x00000400 // GPTM Timer B capture event
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// Interrupt clear
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#define GPTIMER_ICR_CBECINT_M 0x00000400
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#define GPTIMER_ICR_CBECINT_S 10
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#define GPTIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B capture match
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// interrupt clear
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#define GPTIMER_ICR_CBMCINT_M 0x00000200
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#define GPTIMER_ICR_CBMCINT_S 9
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#define GPTIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B time-out interrupt
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// clear
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#define GPTIMER_ICR_TBTOCINT_M 0x00000100
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#define GPTIMER_ICR_TBTOCINT_S 8
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#define GPTIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A match interrupt
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// clear
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#define GPTIMER_ICR_TAMCINT_M 0x00000010
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#define GPTIMER_ICR_TAMCINT_S 4
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#define GPTIMER_ICR_CAECINT 0x00000004 // GPTM Timer A capture event
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// Interrupt clear
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#define GPTIMER_ICR_CAECINT_M 0x00000004
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#define GPTIMER_ICR_CAECINT_S 2
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#define GPTIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A capture match
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// interrupt clear
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#define GPTIMER_ICR_CAMCINT_M 0x00000002
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#define GPTIMER_ICR_CAMCINT_S 1
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#define GPTIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A time-out interrupt
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// clear
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#define GPTIMER_ICR_TATOCINT_M 0x00000001
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#define GPTIMER_ICR_TATOCINT_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// GPTIMER_O_TAILR register.
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//
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//*****************************************************************************
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#define GPTIMER_TAILR_TAILR_M 0xFFFFFFFF // GPTM A interval load register
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#define GPTIMER_TAILR_TAILR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// GPTIMER_O_TBILR register.
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//
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//*****************************************************************************
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#define GPTIMER_TBILR_TBILR_M 0x0000FFFF // GPTM B interval load register
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#define GPTIMER_TBILR_TBILR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// GPTIMER_O_TAMATCHR register.
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//
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//*****************************************************************************
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#define GPTIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A match register
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#define GPTIMER_TAMATCHR_TAMR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// GPTIMER_O_TBMATCHR register.
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//
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//*****************************************************************************
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#define GPTIMER_TBMATCHR_TBMR_M 0x0000FFFF // GPTM Timer B match register
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#define GPTIMER_TBMATCHR_TBMR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TAPR register.
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//
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//*****************************************************************************
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#define GPTIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A prescale
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#define GPTIMER_TAPR_TAPSR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TBPR register.
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//
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//*****************************************************************************
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#define GPTIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B prescale
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#define GPTIMER_TBPR_TBPSR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// GPTIMER_O_TAPMR register.
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//
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//*****************************************************************************
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#define GPTIMER_TAPMR_TAPSR_M 0x000000FF // GPTM Timer A prescale match
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#define GPTIMER_TAPMR_TAPSR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// GPTIMER_O_TBPMR register.
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//
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//*****************************************************************************
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#define GPTIMER_TBPMR_TBPSR_M 0x000000FF // GPTM Timer B prescale match
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#define GPTIMER_TBPMR_TBPSR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TAR register.
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//
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//*****************************************************************************
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#define GPTIMER_TAR_TAR_M 0xFFFFFFFF // GPTM Timer A register
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#define GPTIMER_TAR_TAR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TBR register.
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//
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//*****************************************************************************
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#define GPTIMER_TBR_TBR_M 0x0000FFFF // GPTM Timer B register
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#define GPTIMER_TBR_TBR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TAV register.
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//
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//*****************************************************************************
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#define GPTIMER_TAV_TAV_M 0xFFFFFFFF // GPTM Timer A register
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#define GPTIMER_TAV_TAV_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TBV register.
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//
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//*****************************************************************************
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#define GPTIMER_TBV_PRE_M 0x00FF0000 // GPTM Timer B prescale register
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// (16-bit mode)
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#define GPTIMER_TBV_PRE_S 16
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#define GPTIMER_TBV_TBV_M 0x0000FFFF // GPTM Timer B register
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#define GPTIMER_TBV_TBV_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TAPS register.
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//
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//*****************************************************************************
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#define GPTIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A prescaler
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#define GPTIMER_TAPS_PSS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TBPS register.
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//
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//*****************************************************************************
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#define GPTIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer B prescaler
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#define GPTIMER_TBPS_PSS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TAPV register.
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//
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//*****************************************************************************
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#define GPTIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A prescaler value
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#define GPTIMER_TAPV_PSV_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_TBPV register.
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//
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//*****************************************************************************
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#define GPTIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B prescaler value
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#define GPTIMER_TBPV_PSV_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPTIMER_O_PP register.
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//
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//*****************************************************************************
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#define GPTIMER_PP_ALTCLK 0x00000040 // Alternate clock source 0: Timer
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// is not capable of using an
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// alternate clock. 1: Timer is
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// capable of using an alternate
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// clock.
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#define GPTIMER_PP_ALTCLK_M 0x00000040
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#define GPTIMER_PP_ALTCLK_S 6
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#define GPTIMER_PP_SYNCNT 0x00000020 // Synchronized start 0: Timer is
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// not capable of synchronizing the
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// count value with other timers.
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// 1: Timer is capable of
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// synchronizing the count value
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// with other timers.
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#define GPTIMER_PP_SYNCNT_M 0x00000020
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#define GPTIMER_PP_SYNCNT_S 5
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#define GPTIMER_PP_CHAIN 0x00000010 // Chain with other timers 0:
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// Timer is not capable of chaining
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// with previously numbered Timers.
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// 1: Timer is capable of chaining
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// with previously numbered timers.
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#define GPTIMER_PP_CHAIN_M 0x00000010
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#define GPTIMER_PP_CHAIN_S 4
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#define GPTIMER_PP_SIZE_M 0x0000000F // Timer size 0: Timer A and Timer
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// B are 16 bits wide with 8-bit
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// prescale. 1: Timer A and Timer B
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// are 32 bits wide with 16-bit
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// prescale.
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#define GPTIMER_PP_SIZE_S 0
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#endif // __HW_GPTIMER_H__
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