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https://github.com/RIOT-OS/RIOT.git
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df5c319978
Provide a common clock initialization driver rather than leaving clock initialization to the boards code. A declarative description of the board's clock configuration using a struct does still allow to fine-tune settings. In addition, a board is still allowed to just provide a custom `void clock_init(void)` if there really is the need to do crazy things.
101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
/*
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* Copyright (C) 2014 INRIA
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* 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_z1
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* @{
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*
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* @file
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* @brief Zolertia Z1 peripheral configuration
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*
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "macros/units.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CLOCK_CORECLOCK MHZ(8)
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/**
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* @brief Clock configuration
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*/
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static const msp430_fxyz_clock_params_t clock_params = {
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.xt2_frequency = CLOCK_CORECLOCK,
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.lfxt1_frequency = 32768,
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.main_clock_source = MAIN_CLOCK_SOURCE_XT2CLK,
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.submain_clock_source = SUBMAIN_CLOCK_SOURCE_XT2CLK,
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.main_clock_divier = MAIN_CLOCK_DIVIDE_BY_1,
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.submain_clock_divier = SUBMAIN_CLOCK_DIVIDE_BY_1,
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.auxiliary_clock_divier = AUXILIARY_CLOCK_DIVIDE_BY_1,
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};
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/**
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* @name Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (1U)
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#define TIMER_BASE (TIMER_A)
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#define TIMER_CHAN (3)
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#define TIMER_ISR_CC0 (TIMERA0_VECTOR)
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#define TIMER_ISR_CCX (TIMERA1_VECTOR)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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#define UART_NUMOF (1U)
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#define UART_USE_USCI
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#define UART_BASE (USCI_0)
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#define UART_IE (SFR->IE2)
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#define UART_IF (SFR->IFG2)
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#define UART_IE_RX_BIT (1 << 0)
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#define UART_IE_TX_BIT (1 << 1)
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#define UART_RX_PORT ((msp_port_t *)PORT_3)
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#define UART_RX_PIN (1 << 5)
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#define UART_TX_PORT ((msp_port_t *)PORT_3)
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#define UART_TX_PIN (1 << 4)
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#define UART_RX_ISR (USCIAB0RX_VECTOR)
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#define UART_TX_ISR (USCIAB0TX_VECTOR)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (1U)
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/* SPI configuration */
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#define SPI_USE_USCI
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#define SPI_BASE (USCI_0_B_SPI)
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#define SPI_IE (SFR->IE2)
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#define SPI_IF (SFR->IFG2)
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#define SPI_IE_RX_BIT (1 << 2)
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#define SPI_IE_TX_BIT (1 << 3)
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#define SPI_PIN_MISO GPIO_PIN(P3, 2)
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#define SPI_PIN_MOSI GPIO_PIN(P3, 1)
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#define SPI_PIN_CLK GPIO_PIN(P3, 3)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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