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https://github.com/RIOT-OS/RIOT.git
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a0ac2384ac
All the more recent vendor files have them, so include them for samr30 too. It is expected for this to become obsolete with the next vendor file update.
617 lines
33 KiB
C
617 lines
33 KiB
C
/**
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* \file
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*
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* \brief Header file for SAMR30G18A
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*
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* Copyright (c) 2017 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMR30G18A_
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#define _SAMR30G18A_
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/**
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* \ingroup SAMR30_definitions
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* \addtogroup SAMR30G18A_definitions SAMR30G18A definitions
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* This file defines all structures and symbols for SAMR30G18A:
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* - registers and bitfields
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* - peripheral base address
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* - peripheral ID
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* - PIO definitions
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*/
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/*@{*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#include <stdint.h>
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#ifndef __cplusplus
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typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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#else
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typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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#endif
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typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
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typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
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typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
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typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
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#define CAST(type, value) ((type *)(value))
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#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
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#else
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#define CAST(type, value) (value)
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#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
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#endif
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#if !defined(SKIP_INTEGER_LITERALS)
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#if defined(_U_) || defined(_L_) || defined(_UL_)
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#error "Integer Literals macros already defined elsewhere"
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#endif
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
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#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
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#define _L_(x) x ## L /**< C code: Long integer literal constant value */
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#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
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#else /* Assembler */
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#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
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#define _L_(x) x /**< Assembler: Long integer literal constant value */
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#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* SKIP_INTEGER_LITERALS */
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/* ************************************************************************** */
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/** CMSIS DEFINITIONS FOR SAMR30G18A */
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/* ************************************************************************** */
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/** \defgroup SAMR30G18A_cmsis CMSIS Definitions */
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/*@{*/
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/** Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
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NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
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SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
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PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
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SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
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/****** SAMR30G18A-specific Interrupt Numbers ***********************/
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SYSTEM_IRQn = 0, /**< 0 SAMR30G18A System Interrupts */
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WDT_IRQn = 1, /**< 1 SAMR30G18A Watchdog Timer (WDT) */
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RTC_IRQn = 2, /**< 2 SAMR30G18A Real-Time Counter (RTC) */
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EIC_IRQn = 3, /**< 3 SAMR30G18A External Interrupt Controller (EIC) */
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NVMCTRL_IRQn = 4, /**< 4 SAMR30G18A Non-Volatile Memory Controller (NVMCTRL) */
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DMAC_IRQn = 5, /**< 5 SAMR30G18A Direct Memory Access Controller (DMAC) */
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USB_IRQn = 6, /**< 6 SAMR30G18A Universal Serial Bus (USB) */
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EVSYS_IRQn = 7, /**< 7 SAMR30G18A Event System Interface (EVSYS) */
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SERCOM0_IRQn = 8, /**< 8 SAMR30G18A Serial Communication Interface 0 (SERCOM0) */
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SERCOM1_IRQn = 9, /**< 9 SAMR30G18A Serial Communication Interface 1 (SERCOM1) */
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SERCOM2_IRQn = 10, /**< 10 SAMR30G18A Serial Communication Interface 2 (SERCOM2) */
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SERCOM3_IRQn = 11, /**< 11 SAMR30G18A Serial Communication Interface 3 (SERCOM3) */
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SERCOM4_IRQn = 12, /**< 12 SAMR30G18A Serial Communication Interface 4 (SERCOM4) */
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SERCOM5_IRQn = 13, /**< 13 SAMR30G18A Serial Communication Interface 5 (SERCOM5) */
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TCC0_IRQn = 14, /**< 14 SAMR30G18A Timer Counter Control 0 (TCC0) */
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TCC1_IRQn = 15, /**< 15 SAMR30G18A Timer Counter Control 1 (TCC1) */
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TCC2_IRQn = 16, /**< 16 SAMR30G18A Timer Counter Control 2 (TCC2) */
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TC0_IRQn = 17, /**< 17 SAMR30G18A Basic Timer Counter 0 (TC0) */
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TC1_IRQn = 18, /**< 18 SAMR30G18A Basic Timer Counter 1 (TC1) */
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TC4_IRQn = 21, /**< 21 SAMR30G18A Basic Timer Counter 4 (TC4) */
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ADC_IRQn = 22, /**< 22 SAMR30G18A Analog Digital Converter (ADC) */
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AC_IRQn = 23, /**< 23 SAMR30G18A Analog Comparators (AC) */
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PTC_IRQn = 25, /**< 25 SAMR30G18A Peripheral Touch Controller (PTC) */
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PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
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} IRQn_Type;
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typedef struct _DeviceVectors
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{
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/* Stack pointer */
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void* pvStack;
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/* Cortex-M handlers */
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void* pfnReset_Handler;
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void* pfnNMI_Handler;
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void* pfnHardFault_Handler;
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void* pvReservedM12;
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void* pvReservedM11;
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void* pvReservedM10;
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void* pvReservedM9;
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void* pvReservedM8;
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void* pvReservedM7;
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void* pvReservedM6;
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void* pfnSVC_Handler;
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void* pvReservedM4;
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void* pvReservedM3;
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void* pfnPendSV_Handler;
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void* pfnSysTick_Handler;
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/* Peripheral handlers */
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void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
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void* pfnWDT_Handler; /* 1 Watchdog Timer */
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void* pfnRTC_Handler; /* 2 Real-Time Counter */
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void* pfnEIC_Handler; /* 3 External Interrupt Controller */
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void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */
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void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */
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void* pfnUSB_Handler; /* 6 Universal Serial Bus */
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void* pfnEVSYS_Handler; /* 7 Event System Interface */
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void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */
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void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */
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void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */
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void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */
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void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */
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void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */
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void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */
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void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */
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void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */
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void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */
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void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */
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void* pvReserved19;
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void* pvReserved20;
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void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */
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void* pfnADC_Handler; /* 22 Analog Digital Converter */
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void* pfnAC_Handler; /* 23 Analog Comparators */
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void* pvReserved24;
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void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */
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void* pvReserved26;
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void* pvReserved27;
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void* pvReserved28;
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} DeviceVectors;
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/* Cortex-M0+ processor handlers */
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void Reset_Handler ( void );
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void NMI_Handler ( void );
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void HardFault_Handler ( void );
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void SVC_Handler ( void );
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void PendSV_Handler ( void );
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void SysTick_Handler ( void );
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/* Peripherals handlers */
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void SYSTEM_Handler ( void );
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void WDT_Handler ( void );
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void RTC_Handler ( void );
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void EIC_Handler ( void );
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void NVMCTRL_Handler ( void );
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void DMAC_Handler ( void );
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void USB_Handler ( void );
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void EVSYS_Handler ( void );
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void SERCOM0_Handler ( void );
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void SERCOM1_Handler ( void );
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void SERCOM2_Handler ( void );
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void SERCOM3_Handler ( void );
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void SERCOM4_Handler ( void );
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void SERCOM5_Handler ( void );
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void TCC0_Handler ( void );
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void TCC1_Handler ( void );
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void TCC2_Handler ( void );
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void TC0_Handler ( void );
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void TC1_Handler ( void );
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void TC4_Handler ( void );
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void ADC_Handler ( void );
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void AC_Handler ( void );
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void PTC_Handler ( void );
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/*
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* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
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*/
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#define LITTLE_ENDIAN 1
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#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
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#define __VTOR_PRESENT 1 /*!< VTOR present or not */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* \brief CMSIS includes
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*/
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#include <core_cm0plus.h>
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#if !defined DONT_USE_CMSIS_INIT
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#include "system_samr30.h"
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#endif /* DONT_USE_CMSIS_INIT */
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/*@}*/
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/* ************************************************************************** */
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/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR30G18A */
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/* ************************************************************************** */
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/** \defgroup SAMR30G18A_api Peripheral Software API */
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/*@{*/
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#include "component/ac.h"
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#include "component/adc.h"
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#include "component/ccl.h"
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#include "component/dmac.h"
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#include "component/dsu.h"
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#include "component/eic.h"
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#include "component/evsys.h"
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#include "component/gclk.h"
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#include "component/mclk.h"
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#include "component/mtb.h"
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#include "component/nvmctrl.h"
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#include "component/oscctrl.h"
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#include "component/osc32kctrl.h"
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#include "component/pac.h"
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#include "component/pm.h"
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#include "component/port.h"
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#include "component/rstc.h"
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#include "component/rtc.h"
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#include "component/rfctrl.h"
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#include "component/sercom.h"
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#include "component/supc.h"
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#include "component/tal.h"
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#include "component/tc.h"
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#include "component/tcc.h"
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#include "component/usb.h"
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#include "component/wdt.h"
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/*@}*/
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/* ************************************************************************** */
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/** REGISTERS ACCESS DEFINITIONS FOR SAMR30G18A */
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/* ************************************************************************** */
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/** \defgroup SAMR30G18A_reg Registers Access Definitions */
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/*@{*/
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#include "instance/ac.h"
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#include "instance/adc.h"
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#include "instance/ccl.h"
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#include "instance/dmac.h"
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#include "instance/dsu.h"
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#include "instance/eic.h"
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#include "instance/evsys.h"
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#include "instance/gclk.h"
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#include "instance/mclk.h"
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#include "instance/mtb.h"
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#include "instance/nvmctrl.h"
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#include "instance/oscctrl.h"
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#include "instance/osc32kctrl.h"
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#include "instance/pac.h"
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#include "instance/pm.h"
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#include "instance/port.h"
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#include "instance/rstc.h"
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#include "instance/rtc.h"
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#include "instance/rfctrl.h"
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#include "instance/sercom0.h"
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#include "instance/sercom1.h"
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#include "instance/sercom2.h"
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#include "instance/sercom3.h"
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#include "instance/sercom4.h"
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#include "instance/sercom5.h"
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#include "instance/supc.h"
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#include "instance/tal.h"
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#include "instance/tc0.h"
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#include "instance/tc1.h"
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#include "instance/tc4.h"
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#include "instance/tcc0.h"
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#include "instance/tcc1.h"
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#include "instance/tcc2.h"
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#include "instance/usb.h"
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#include "instance/wdt.h"
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/*@}*/
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/* ************************************************************************** */
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/** PERIPHERAL ID DEFINITIONS FOR SAMR30G18A */
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/* ************************************************************************** */
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/** \defgroup SAMR30G18A_id Peripheral Ids Definitions */
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/*@{*/
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// Peripheral instances on HPB0 bridge
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#define ID_PM 0 /**< \brief Power Manager (PM) */
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#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */
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#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */
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#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */
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#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */
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#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */
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#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */
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#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */
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#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */
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#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */
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#define ID_PORT 10 /**< \brief Port Module (PORT) */
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#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */
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// Peripheral instances on HPB1 bridge
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#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */
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#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
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#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
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#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
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// Peripheral instances on HPB2 bridge
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#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */
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#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */
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#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */
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#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */
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#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */
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#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */
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#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */
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#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */
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#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */
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#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */
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// Peripheral instances on HPB3 bridge
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#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */
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#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
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#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */
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#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */
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#define ID_AC 100 /**< \brief Analog Comparators (AC) */
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#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */
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#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */
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// Peripheral instances on HPB4 bridge
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#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */
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#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */
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#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */
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/*@}*/
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/* ************************************************************************** */
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/** BASE ADDRESS DEFINITIONS FOR SAMR30G18A */
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/* ************************************************************************** */
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/** \defgroup SAMR30G18A_base Peripheral Base Address Definitions */
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/*@{*/
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#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
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#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */
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#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */
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#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */
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#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */
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#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
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#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */
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#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */
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#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */
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#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */
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#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
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#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
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#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
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#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
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#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
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#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */
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#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */
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#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
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#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
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#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
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#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */
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#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */
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#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */
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#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */
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#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */
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#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
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#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */
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#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */
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#define RFCTRL (0x42003C00UL) /**< \brief (RFCTRL) APB Base Address */
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#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */
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#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */
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#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */
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#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */
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#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */
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#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
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#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */
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#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */
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#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */
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#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */
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#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */
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#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */
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#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */
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#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */
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#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */
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#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */
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#else
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#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */
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#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
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#define AC_INSTS { AC } /**< \brief (AC) Instances List */
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#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */
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#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
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#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
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#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
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#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
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#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
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#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */
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#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
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#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
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#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
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#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
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#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
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#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */
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#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
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#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
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#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */
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#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
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#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
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#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
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#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
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#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
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#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */
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#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
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#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
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#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
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#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
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#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
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#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
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#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
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#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
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#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
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#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */
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#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */
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#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
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#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
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#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
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#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
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#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
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#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */
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#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
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#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
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#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */
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#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
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#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
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#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */
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#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
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#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
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#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */
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#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
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#define PM_INSTS { PM } /**< \brief (PM) Instances List */
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#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */
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#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
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#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
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#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
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#define PTC_GCLK_ID 33
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#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
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#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
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#define RFCTRL ((Rfctrl *)0x42003C00U) /**< \brief (RSTC) APB Base Address */
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#define RFCTRL_INST_NUM 1 /**< \brief (RSTC) Number of instances */
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#define RFCTRL_INSTS { RFCTRL } /**< \brief (RSTC) Instances List */
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#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */
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#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
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#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
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#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */
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#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
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#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
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#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */
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#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */
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#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */
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#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */
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#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */
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#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
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#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
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#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
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#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */
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#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
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#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
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#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */
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#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */
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#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */
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#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */
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#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */
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#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */
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#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
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#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */
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#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */
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#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */
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#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
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#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
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#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */
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#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
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#define USB_INSTS { USB } /**< \brief (USB) Instances List */
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#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */
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#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
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#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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/* ************************************************************************** */
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/** PORT DEFINITIONS FOR SAMR30G18A */
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/* ************************************************************************** */
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/** \defgroup SAMR30G18A_port PORT Definitions */
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/*@{*/
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#include "pio/samr30g18a.h"
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/*@}*/
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/* ************************************************************************** */
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/** MEMORY MAPPING DEFINITIONS FOR SAMR30G18A */
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/* ************************************************************************** */
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#define FLASH_SIZE 0x40000UL /* 256 kB */
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#define FLASH_PAGE_SIZE 64
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#define FLASH_NB_OF_PAGES 4096
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#define FLASH_USER_PAGE_SIZE 64
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#define HSRAM_SIZE 0x8000UL /* 32 kB */
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#define LPRAM_SIZE 0x2000UL /* 8 kB */
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#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
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#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
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#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */
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#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */
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#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
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#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
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#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
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#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */
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#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */
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#define PPB_ADDR (0xE0000000u) /**< PPB base address */
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#define DSU_DID_RESETVALUE 0x1081021EUL
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#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */
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#define PORT_GROUPS 3
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#define USB_HOST_IMPLEMENTED 1
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/* ************************************************************************** */
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/** ELECTRICAL DEFINITIONS FOR SAMR30G18A */
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/* ************************************************************************** */
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#ifdef __cplusplus
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}
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#endif
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/*@}*/
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#endif /* SAMR30G18A_H */
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