mirror of
https://github.com/RIOT-OS/RIOT.git
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261 lines
7.8 KiB
C
261 lines
7.8 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_msbiot
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the MSB-IoT board
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*
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (16000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (168000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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#define CLOCK_PLL_M (CLOCK_HSE / 1000000)
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#define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
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#define CLOCK_PLL_P (2U)
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#define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (2U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 1
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#define TIMER_IRQ_PRIO 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV TIM2
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_PRESCALER (83U)
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#define TIMER_0_MAX_VALUE (0xffffffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
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#define TIMER_0_ISR isr_tim2
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#define TIMER_0_IRQ_CHAN TIM2_IRQn
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/* Timer 1 configuration */
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#define TIMER_1_DEV TIM5
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#define TIMER_1_CHANNELS 4
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#define TIMER_1_PRESCALER (83U)
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#define TIMER_1_MAX_VALUE (0xffffffff)
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#define TIMER_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM5EN)
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#define TIMER_1_ISR isr_tim5
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#define TIMER_1_IRQ_CHAN TIM5_IRQn
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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#define PWM_NUMOF (1U)
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#define PWM_0_EN 1
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#define PWM_MAX_CHANNELS 1 /* Increase if Timer with more channels is used */
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/* PWM 0 device configuration */
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#define PWM_0_DEV TIM11
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#define PWM_0_CHANNELS 1
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#define PWM_0_CLK (168000000U)
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#define PWM_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_TIM11EN)
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#define PWM_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_TIM11EN)
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/* PWM 0 pin configuration */
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#define PWM_0_PORT GPIOB
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#define PWM_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define PWM_0_PIN_CH0 9
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#define PWM_0_PIN_AF 3
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_NUMOF (1U)
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#define ADC_0_EN 1
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#define ADC_MAX_CHANNELS 2
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/* ADC 0 configuration */
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#define ADC_0_DEV ADC1
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#define ADC_0_CHANNELS 2
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#define ADC_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_ADC1EN)
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#define ADC_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
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#define ADC_0_PORT GPIOB
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#define ADC_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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/* ADC 0 channel 0 pin config */
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#define ADC_0_CH0 8
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#define ADC_0_CH0_PIN 0
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/* ADC 0 channel 1 pin config */
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#define ADC_0_CH1 9
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#define ADC_0_CH1_PIN 1
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/** @} */
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/**
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* @name DAC configuration
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* @{
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*/
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#define DAC_NUMOF (1U)
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#define DAC_0_EN 1
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#define DAC_MAX_CHANNELS 2
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/* DAC 0 configuration */
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#define DAC_0_DEV DAC
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#define DAC_0_CHANNELS 2
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#define DAC_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
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#define DAC_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
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#define DAC_0_PORT GPIOA
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#define DAC_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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/* DAC 0 channel config */
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#define DAC_0_CH0_PIN 4
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#define DAC_0_CH1_PIN 5
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/** @} */
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/**
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* @name Random Number Generator configuration
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* @{
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*/
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#define RANDOM_NUMOF (1U)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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#define UART_NUMOF (3U)
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#define UART_0_EN 1
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#define UART_1_EN 1
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#define UART_2_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART2
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#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
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#define UART_0_CLK (42000000) /* UART clock runs with 42MHz (F_CPU / 4) */
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#define UART_0_IRQ_CHAN USART2_IRQn
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#define UART_0_ISR isr_usart2
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/* UART 0 pin configuration */
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#define UART_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define UART_0_PORT GPIOA
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#define UART_0_TX_PIN 2
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#define UART_0_RX_PIN 3
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#define UART_0_AF 7
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/* UART 1 device configuration */
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#define UART_1_DEV USART1
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#define UART_1_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
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#define UART_1_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
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#define UART_1_CLK (84000000) /* UART clock runs with 84MHz (F_CPU / 2) */
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#define UART_1_IRQ_CHAN USART1_IRQn
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#define UART_1_ISR isr_usart1
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/* UART 1 pin configuration */
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#define UART_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define UART_1_PORT GPIOA
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#define UART_1_TX_PIN 9
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#define UART_1_RX_PIN 10
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#define UART_1_AF 7
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/* UART 2 device configuration */
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#define UART_2_DEV USART3
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#define UART_2_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
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#define UART_2_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
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#define UART_2_CLK (42000000) /* UART clock runs with 42MHz (F_CPU / 4) */
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#define UART_2_IRQ_CHAN USART3_IRQn
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#define UART_2_ISR isr_usart3
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/* UART 2 pin configuration */
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#define UART_2_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN)
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#define UART_2_PORT GPIOD
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#define UART_2_TX_PIN 8
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#define UART_2_RX_PIN 9
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#define UART_2_AF 7
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF 1
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#define SPI_0_EN 1
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#define SPI_1_EN 0
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#define SPI_IRQ_PRIO 1
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/* SPI 0 device config */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
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#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_IRQ_HANDLER isr_spi1
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/* SPI 0 pin configuration */
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#define SPI_0_SCK_PORT GPIOA
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#define SPI_0_SCK_PIN 5
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#define SPI_0_SCK_AF 5
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#define SPI_0_MISO_PORT GPIOA
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#define SPI_0_MISO_PIN 6
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#define SPI_0_MISO_AF 5
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#define SPI_0_MOSI_PORT GPIOA
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#define SPI_0_MOSI_PIN 7
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#define SPI_0_MOSI_AF 5
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#define SPI_0_SCK_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define SPI_0_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_0_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (42000000U)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
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#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_SCL_PORT GPIOB
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#define I2C_0_SCL_PIN 6
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#define I2C_0_SCL_AF 4
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#define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define I2C_0_SDA_PORT GPIOB
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#define I2C_0_SDA_PIN 7
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#define I2C_0_SDA_AF 4
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#define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H_ */
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/** @} */
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