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Koen Zandberg
32399901f0
Similar to the cortex-m common linker scripts, the RISC-V linker scripts can be unified easily, requiring only the memory addresses and lengths. This simplifies adding new RISC-V CPU's later
24 lines
576 B
Plaintext
24 lines
576 B
Plaintext
/*
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* Copyright (C) 2020 Inria
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* 2020 Koen Zandberg <koen@bergzand.net
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_fe310
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* @{
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*
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* @file
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* @brief Linker variables for SiFive FE310
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*
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* @author Koen Zandberg <koen@bergzand.net>
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*
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* @}
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*/
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_itim_start_addr = DEFINED( _itim_start_addr ) ? _itim_start_addr : 0x0;
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_itim_length = DEFINED( _itim_length ) ? _itim_length : 0x0;
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