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https://github.com/RIOT-OS/RIOT.git
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448 lines
25 KiB
C
448 lines
25 KiB
C
/***************************************************************************//**
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* @file
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* @brief CMSIS Cortex-M Peripheral Access Layer Header File
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* for EFR32MG1P132F256GM32
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*******************************************************************************
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* # License
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* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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******************************************************************************/
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#if defined(__ICCARM__)
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#pragma system_include /* Treat file as system include file. */
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang system_header /* Treat file as system include file. */
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#endif
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#ifndef EFR32MG1P132F256GM32_H
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#define EFR32MG1P132F256GM32_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @defgroup EFR32MG1P132F256GM32 EFR32MG1P132F256GM32
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* @{
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******************************************************************************/
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/** Interrupt Number Definition */
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typedef enum IRQn{
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/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
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EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
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FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
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WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
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FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
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MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
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RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
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RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
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BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
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LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
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GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
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TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
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USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
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USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
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ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
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ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
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IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
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I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
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GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
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TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
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USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
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USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
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LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
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PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
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CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
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MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
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CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
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LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
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AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
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PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
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RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
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SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
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CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
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RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
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FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
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} IRQn_Type;
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/***************************************************************************//**
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* @defgroup EFR32MG1P132F256GM32_Core Core
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* @{
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* @brief Processor and Core Peripheral Section
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******************************************************************************/
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#define __MPU_PRESENT 1U /**< Presence of MPU */
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#define __FPU_PRESENT 1U /**< Presence of FPU */
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#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
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#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
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#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
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/** @} End of group EFR32MG1P132F256GM32_Core */
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/***************************************************************************//**
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* @defgroup EFR32MG1P132F256GM32_Part Part
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* @{
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******************************************************************************/
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/** Part family */
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#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
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#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
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#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
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#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
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#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
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#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
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#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
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#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
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#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
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#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
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#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
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#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
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#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
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#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
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#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
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#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
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/* If part number is not defined as compiler option, define it */
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#if !defined(EFR32MG1P132F256GM32)
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#define EFR32MG1P132F256GM32 1 /**< MIGHTY Gecko Part */
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#endif
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/** Configure part number */
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#define PART_NUMBER "EFR32MG1P132F256GM32" /**< Part Number */
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/** Memory Base addresses and limits */
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#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
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#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
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#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
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#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
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#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
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#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
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#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
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#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
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#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
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#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
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#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
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#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
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#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
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#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
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#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
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#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
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#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
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#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
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#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
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#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
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#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
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#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
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#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
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#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
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#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
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#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
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#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
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#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
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#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
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#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
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#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
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#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
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#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
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#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
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#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
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#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
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/** Bit banding area */
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#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
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#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
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/** Flash and SRAM limits for EFR32MG1P132F256GM32 */
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#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
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#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
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#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
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#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
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#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
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#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
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#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
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#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
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#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
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/** AF channels connect the different on-chip peripherals with the af-mux */
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#define AFCHAN_MAX 72U
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/** AF channel maximum location number */
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#define AFCHANLOC_MAX 32U
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/** Analog AF channels */
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#define AFACHAN_MAX 61U
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/* Part number capabilities */
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#define TIMER_PRESENT /**< TIMER is available in this part */
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#define TIMER_COUNT 2 /**< 2 TIMERs available */
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#define USART_PRESENT /**< USART is available in this part */
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#define USART_COUNT 2 /**< 2 USARTs available */
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#define LEUART_PRESENT /**< LEUART is available in this part */
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#define LEUART_COUNT 1 /**< 1 LEUARTs available */
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#define LETIMER_PRESENT /**< LETIMER is available in this part */
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#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
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#define PCNT_PRESENT /**< PCNT is available in this part */
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#define PCNT_COUNT 1 /**< 1 PCNTs available */
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#define I2C_PRESENT /**< I2C is available in this part */
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#define I2C_COUNT 1 /**< 1 I2Cs available */
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#define ADC_PRESENT /**< ADC is available in this part */
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#define ADC_COUNT 1 /**< 1 ADCs available */
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#define ACMP_PRESENT /**< ACMP is available in this part */
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#define ACMP_COUNT 2 /**< 2 ACMPs available */
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#define IDAC_PRESENT /**< IDAC is available in this part */
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#define IDAC_COUNT 1 /**< 1 IDACs available */
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#define WDOG_PRESENT /**< WDOG is available in this part */
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#define WDOG_COUNT 1 /**< 1 WDOGs available */
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#define MSC_PRESENT /**< MSC is available in this part */
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#define MSC_COUNT 1 /**< 1 MSC available */
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#define EMU_PRESENT /**< EMU is available in this part */
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#define EMU_COUNT 1 /**< 1 EMU available */
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#define RMU_PRESENT /**< RMU is available in this part */
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#define RMU_COUNT 1 /**< 1 RMU available */
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#define CMU_PRESENT /**< CMU is available in this part */
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#define CMU_COUNT 1 /**< 1 CMU available */
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#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
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#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
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#define GPIO_PRESENT /**< GPIO is available in this part */
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#define GPIO_COUNT 1 /**< 1 GPIO available */
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#define PRS_PRESENT /**< PRS is available in this part */
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#define PRS_COUNT 1 /**< 1 PRS available */
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#define LDMA_PRESENT /**< LDMA is available in this part */
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#define LDMA_COUNT 1 /**< 1 LDMA available */
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#define FPUEH_PRESENT /**< FPUEH is available in this part */
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#define FPUEH_COUNT 1 /**< 1 FPUEH available */
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#define GPCRC_PRESENT /**< GPCRC is available in this part */
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#define GPCRC_COUNT 1 /**< 1 GPCRC available */
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#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
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#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
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#define RTCC_PRESENT /**< RTCC is available in this part */
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#define RTCC_COUNT 1 /**< 1 RTCC available */
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#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
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#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
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#define DCDC_PRESENT /**< DCDC is available in this part */
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#define DCDC_COUNT 1 /**< 1 DCDC available */
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#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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#include "system_efr32mg1p.h" /* System Header File */
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/** @} End of group EFR32MG1P132F256GM32_Part */
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/***************************************************************************//**
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* @defgroup EFR32MG1P132F256GM32_Peripheral_TypeDefs Peripheral TypeDefs
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* @{
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* @brief Device Specific Peripheral Register Structures
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******************************************************************************/
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#include "efr32mg1p_msc.h"
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#include "efr32mg1p_emu.h"
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#include "efr32mg1p_rmu.h"
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#include "efr32mg1p_cmu.h"
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#include "efr32mg1p_crypto.h"
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#include "efr32mg1p_gpio_p.h"
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#include "efr32mg1p_gpio.h"
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#include "efr32mg1p_prs_ch.h"
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#include "efr32mg1p_prs.h"
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#include "efr32mg1p_ldma_ch.h"
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#include "efr32mg1p_ldma.h"
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#include "efr32mg1p_fpueh.h"
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#include "efr32mg1p_gpcrc.h"
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#include "efr32mg1p_timer_cc.h"
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#include "efr32mg1p_timer.h"
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#include "efr32mg1p_usart.h"
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#include "efr32mg1p_leuart.h"
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#include "efr32mg1p_letimer.h"
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#include "efr32mg1p_cryotimer.h"
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#include "efr32mg1p_pcnt.h"
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#include "efr32mg1p_i2c.h"
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#include "efr32mg1p_adc.h"
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#include "efr32mg1p_acmp.h"
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#include "efr32mg1p_idac.h"
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#include "efr32mg1p_rtcc_cc.h"
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#include "efr32mg1p_rtcc_ret.h"
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#include "efr32mg1p_rtcc.h"
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#include "efr32mg1p_wdog_pch.h"
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#include "efr32mg1p_wdog.h"
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#include "efr32mg1p_dma_descriptor.h"
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#include "efr32mg1p_devinfo.h"
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#include "efr32mg1p_romtable.h"
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/** @} End of group EFR32MG1P132F256GM32_Peripheral_TypeDefs */
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/***************************************************************************//**
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* @defgroup EFR32MG1P132F256GM32_Peripheral_Base Peripheral Memory Map
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* @{
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******************************************************************************/
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#define MSC_BASE (0x400E0000UL) /**< MSC base address */
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#define EMU_BASE (0x400E3000UL) /**< EMU base address */
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#define RMU_BASE (0x400E5000UL) /**< RMU base address */
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#define CMU_BASE (0x400E4000UL) /**< CMU base address */
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#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
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#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
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#define PRS_BASE (0x400E6000UL) /**< PRS base address */
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#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
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#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
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#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
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#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
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#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
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#define USART0_BASE (0x40010000UL) /**< USART0 base address */
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#define USART1_BASE (0x40010400UL) /**< USART1 base address */
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#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
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#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
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#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
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#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
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#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
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#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
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#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
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#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
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#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
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#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
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#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
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#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
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#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
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#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
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#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
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/** @} End of group EFR32MG1P132F256GM32_Peripheral_Base */
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/***************************************************************************//**
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* @defgroup EFR32MG1P132F256GM32_Peripheral_Declaration Peripheral Declarations
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* @{
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******************************************************************************/
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#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
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#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
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#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
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#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
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#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
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#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
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#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
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#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
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#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
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#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
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#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
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#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
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#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
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#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
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#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
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#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
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#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
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#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
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#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
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#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
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#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
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#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
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#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
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#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
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#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
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#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
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#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
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/** @} End of group EFR32MG1P132F256GM32_Peripheral_Declaration */
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/***************************************************************************//**
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* @defgroup EFR32MG1P132F256GM32_Peripheral_Offsets Peripheral Offsets
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* @{
|
|
******************************************************************************/
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|
|
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#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
|
|
#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
|
|
#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
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|
#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
|
|
#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
|
|
#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
|
|
#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
|
|
#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
|
|
#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
|
|
#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
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|
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/** @} End of group EFR32MG1P132F256GM32_Peripheral_Offsets */
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|
|
|
/***************************************************************************//**
|
|
* @defgroup EFR32MG1P132F256GM32_BitFields Bit Fields
|
|
* @{
|
|
******************************************************************************/
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|
|
|
#include "efr32mg1p_prs_signals.h"
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|
#include "efr32mg1p_dmareq.h"
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|
|
|
/***************************************************************************//**
|
|
* @defgroup EFR32MG1P132F256GM32_UNLOCK Unlock Codes
|
|
* @{
|
|
******************************************************************************/
|
|
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
|
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
|
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
|
|
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
|
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
|
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
|
#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
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|
|
|
/** @} End of group EFR32MG1P132F256GM32_UNLOCK */
|
|
|
|
/** @} End of group EFR32MG1P132F256GM32_BitFields */
|
|
|
|
#include "efr32mg1p_af_ports.h"
|
|
#include "efr32mg1p_af_pins.h"
|
|
|
|
/***************************************************************************//**
|
|
* @brief Set the value of a bit field within a register.
|
|
*
|
|
* @param REG
|
|
* The register to update
|
|
* @param MASK
|
|
* The mask for the bit field to update
|
|
* @param VALUE
|
|
* The value to write to the bit field
|
|
* @param OFFSET
|
|
* The number of bits that the field is offset within the register.
|
|
* 0 (zero) means LSB.
|
|
******************************************************************************/
|
|
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
|
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
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|
|
|
/** @} End of group EFR32MG1P132F256GM32 */
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|
|
|
/** @} End of group Parts */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif /* EFR32MG1P132F256GM32_H */
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