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a73f3809cc
The CC26x2 and CC13x2 share the same register definitions, and both are treated equally in the TI's technical reference manual. [1] - To avoid confusions in the future I renamed it to `cc26x2_cc13x2`. - Documentation was updated. - The `cc1312-launchpad` board that uses the `cc13x2` MCU was updated. - The `cc1352-launchpad` board that uses the `cc13x2` MCU was updated. [1]: https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
347 lines
12 KiB
C
347 lines
12 KiB
C
/*
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* Copyright (C) 2016 Leon George
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* Copyright (C) 2018 Anton Gerasimov
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_cc26x2_cc13x2_definitions
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* @{
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*
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* @file
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* @brief CC26x2, CC13x2 AUX register definitions
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*/
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#ifndef CC26X2_CC13X2_AUX_H
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#define CC26X2_CC13X2_AUX_H
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#include <stdbool.h>
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#include "cc26xx_cc13xx.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* AUX_AIODIO registers
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*/
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typedef struct {
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reg32_t IOMODE; /**< input output mode */
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reg32_t GPIODIE; /**< gpio data input enable */
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reg32_t IOPOE; /**< io peripheral output enable */
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reg32_t GPIODOUT; /**< gpio data output */
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reg32_t GPIODIN; /**< gpio data input */
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reg32_t GPIODOUTSET; /**< gpio data out set */
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reg32_t GPIODOUTCLR; /**< gpio data out clear */
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reg32_t GPIODOUTTGL; /**< gpio data out toggle */
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reg32_t IO0PSEL; /**< i/o 0 peripheral select */
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reg32_t IO1PSEL; /**< i/o 1 peripheral select */
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reg32_t IO2PSEL; /**< i/o 2 peripheral select */
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reg32_t IO3PSEL; /**< i/o 3 peripheral select */
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reg32_t IO4PSEL; /**< i/o 4 peripheral select */
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reg32_t IO5PSEL; /**< i/o 5 peripheral select */
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reg32_t IO6PSEL; /**< i/o 6 peripheral select */
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reg32_t IO7PSEL; /**< i/o 7 peripheral select */
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reg32_t IOMODEH; /**< input output mode high */
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reg32_t IOMODEL; /**< input output mode low */
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} aux_aiodio_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_AIODIO0_BASE 0x400CC000 /**< AUX_AIODIO0 base address */
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#define AUX_AIODIO1_BASE 0x400CD000 /**< AUX_AIODIO1 base address */
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#define AUX_AIODIO2_BASE 0x400CE000 /**< AUX_AIODIO2 base address */
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#define AUX_AIODIO3_BASE 0x400CF000 /**< AUX_AIODIO3 base address */
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/** @} */
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#define AUX_AIODIO0 ((aux_aiodio_regs_t *) (AUX_AIODIO0_BASE)) /**< AUX_AIODIO0 register bank */
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#define AUX_AIODIO1 ((aux_aiodio_regs_t *) (AUX_AIODIO1_BASE)) /**< AUX_AIODIO1 register bank */
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#define AUX_AIODIO2 ((aux_aiodio_regs_t *) (AUX_AIODIO2_BASE)) /**< AUX_AIODIO2 register bank */
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#define AUX_AIODIO3 ((aux_aiodio_regs_t *) (AUX_AIODIO3_BASE)) /**< AUX_AIODIO3 register bank */
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/**
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* AUX_TDC registers
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*/
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typedef struct {
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reg32_t CTL; /**< control */
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reg32_t STAT; /**< status */
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reg32_t RESULT; /**< result */
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reg32_t SATCFG; /**< saturaion configuration */
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reg32_t TRIGSRC; /**< trigger source */
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reg32_t TRIGCNT; /**< trigger counter */
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reg32_t TRIGCNTLOAD; /**< trigger counter load */
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reg32_t TRIGCNTCFG; /**< trigger counter config */
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reg32_t PRECTL; /**< prescaler control */
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reg32_t PRECNT; /**< prescaler counter */
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} aux_tdc_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_TDC_BASE 0x400C4000 /**< AUX_TDC base address */
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/** @} */
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#define AUX_TDC ((aux_tdc_regs_t *) (AUX_TDC_BASE)) /**< AUX_TDC register bank */
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/**
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* AUX_EVCTL registers
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*/
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typedef struct {
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reg32_t EVSTAT0; /**< event status 0 */
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reg32_t EVSTAT1; /**< event status 1 */
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reg32_t EVSTAT2; /**< event status 2 */
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reg32_t EVSTAT3; /**< event status 3 */
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reg32_t SCEWEVSEL0; /**< sensor controller engine wait event configuration 0 */
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reg32_t SCEWEVSEL1; /**< sensor controller engine wait event configuration 1 */
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reg32_t DMACTL; /**< direct memoty access control */
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reg32_t __reserved; /**< meh */
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reg32_t SWEVSET; /**< software event set */
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reg32_t EVTOAONFLAGS; /**< events to AON domain flags */
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reg32_t EVTOAONPOL; /**< events to AON domain polarity */
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reg32_t EVTOAONFLAGSCLR; /**< events to AON domain clear */
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reg32_t EVTOMCUFLAGS; /**< event to MCU domain flags */
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reg32_t EVTOMCUPOL; /**< event to MCU domain polarity */
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reg32_t EVTOMCUFLAGSCLR; /**< events to MCU domain flags clear */
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reg32_t COMBEVTOMCUMASK; /**< combined event to MCU domain mask */
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reg32_t PROGDLY; /**< programmable delay */
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reg32_t MANUAL; /**< manual */
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reg32_t EVSTAT0L; /**< event status 0 low */
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reg32_t EVSTAT0H; /**< event status 0 high */
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reg32_t EVSTAT1L; /**< event status 1 low */
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reg32_t EVSTAT1H; /**< event status 1 high */
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reg32_t EVSTAT2L; /**< event status 2 low */
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reg32_t EVSTAT2H; /**< event status 2 high */
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reg32_t EVSTAT3L; /**< event status 3 low */
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reg32_t EVSTAT3H; /**< event status 3 high */
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} aux_evtcl_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_EVCTL_BASE 0x400C5000 /**< AUX_EVCTL base address */
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/** @} */
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#define AUX_EVCTL ((aux_evctl_regs_t *) (AUX_EVCTL_BASE)) /**< AUX_EVCTL register bank */
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/**
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* AUX_SYSIF registers
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*/
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typedef struct {
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reg32_t OPMODEREQ; /**< operational mode request */
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reg32_t OPMODEACK; /**< operational mode acknowledgement */
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reg32_t PROGWU0CFG; /**< programmanble wakeup 0 configuration */
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reg32_t PROGWU1CFG; /**< programmanble wakeup 0 configuration */
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reg32_t PROGWU2CFG; /**< programmanble wakeup 0 configuration */
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reg32_t PROGWU3CFG; /**< programmanble wakeup 0 configuration */
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reg32_t SWUTRIG; /**< software wakeup triggers */
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reg32_t WUFLAGS; /**< wakeup flags */
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reg32_t WUFLAGSCLR; /**< wakeup flags clear */
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reg32_t WUGATE; /**< wakeup gate */
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reg32_t VECCFG0; /**< vector configuration 0 */
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reg32_t VECCFG1; /**< vector configuration 1 */
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reg32_t VECCFG2; /**< vector configuration 2 */
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reg32_t VECCFG3; /**< vector configuration 3 */
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reg32_t VECCFG4; /**< vector configuration 4 */
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reg32_t VECCFG5; /**< vector configuration 5 */
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reg32_t VECCFG6; /**< vector configuration 6 */
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reg32_t VECCFG7; /**< vector configuration 7 */
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reg32_t EVSYNCRATE; /**< event synchronization rate */
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reg32_t PEROPRATE; /**< peripheral operational rate */
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reg32_t ADCCLKCTL; /**< ADC clock control */
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reg32_t TDCCLKCTL; /**< TDC clock control */
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reg32_t TDCREFCLKCTL; /**< TDC reference clock control */
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reg32_t TIMER2CLKCTL; /**< AUX_TIMER2 clock control */
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reg32_t TIMER2CLKSTAT; /**< AUX_TIMER2 clock status */
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reg32_t TIMER2CLKSWITCH; /**< AUX_TIMER2 clock switch */
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reg32_t TIMER2DBGCTL; /**< AUX_TIMER2 debug control */
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reg32_t __reserved1; /**< meh */
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reg32_t CLKSHIFTDET; /**< clock shift detection */
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reg32_t RECHARGETRIG; /**< recharge trigger */
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reg32_t RECHARGEDET; /**< recharge detector */
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reg32_t RTCSUBSECINC0; /**< RTC sub-second increment 0 */
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reg32_t RTCSUBSECINC1; /**< RTC sub-second increment 1 */
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reg32_t RTCSUBSECINCCTL; /**< RTC sub-second increment control */
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reg32_t RTCSEC; /**< RTC second */
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reg32_t RTCSUBSEC; /**< RTC sub-second */
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reg32_t RTCEVCLR; /**< RTC event clear */
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reg32_t BATMONBAT; /**< battery voltage */
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reg32_t __reserved2; /**< meh */
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reg32_t BATMONTEMP; /**< batmon temperature */
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reg32_t TIMERHALT; /**< timer halt */
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reg32_t __reserved3[3]; /**< meh */
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reg32_t TIMER2BRIDGE; /**< timer2 bridge */
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reg32_t SWPWRPROF; /**< software power profiler */
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} aux_sysif_regs_t;
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/** @} */
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_SYSIF_BASE 0x400C6000 /**< AUX_SYSIF base address */
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/** @} */
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#define AUX_SYSIF ((aux_wuc_regs_t *) (AUX_SYSIF_BASE)) /**< AUX_SYSIF register bank */
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/**
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* AUX_TIMER registers
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*/
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typedef struct {
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reg32_t T0CFG; /**< timer 0 config */
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reg32_t T0CTL; /**< timer 0 control */
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reg32_t T0TARGET; /**< timer 0 target */
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reg32_t T0CNTR; /**< timer 0 counter */
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reg32_t T1CFG; /**< timer 1 config */
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reg32_t T1TARGET; /**< timer 1 target */
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reg32_t T1CTL; /**< timer 1 control */
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reg32_t T1CNTR; /**< timer 0 counter */
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} aux_timer01_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_TIMER01_BASE 0x400C7000 /**< AUX_WUC base address */
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/** @} */
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#define AUX_TIMER01 ((aux_timer01_regs_t *) (AUX_TIMER01_BASE)) /**< AUX_TIMER01 register bank */
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/**
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* AUX_TIMER2 registers
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*/
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typedef struct {
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reg32_t CTL; /**< timer 2 control */
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reg32_t TARGET; /**< timer 2 target */
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reg32_t SHDWTARGET; /**< timer 2 shadow target */
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reg32_t CNTR; /**< timer 2 counter */
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reg32_t PRECFG; /**< timer 2 prescaler config */
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reg32_t EVCTL; /**< timer 2 event control */
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reg32_t PULSETRIG; /**< timer 2 pulse trigger */
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reg32_t __reserved[25]; /**< meh */
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reg32_t CH0EVCFG; /**< timer 2 channel 0 event configuration */
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reg32_t CH0CCFG; /**< timer 2 channel 0 capture configuration */
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reg32_t CH0PCC; /**< timer 2 channel 0 pipeline capture compare */
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reg32_t CH0CC; /**< timer 2 channel 0 capture compare */
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reg32_t CH1EVCFG; /**< timer 2 channel 1 event configuration */
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reg32_t CH1CCFG; /**< timer 2 channel 1 capture configuration */
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reg32_t CH1PCC; /**< timer 2 channel 1 pipeline capture compare */
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reg32_t CH1CC; /**< timer 2 channel 1 capture compare */
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reg32_t CH2EVCFG; /**< timer 2 channel 2 event configuration */
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reg32_t CH2CCFG; /**< timer 2 channel 2 capture configuration */
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reg32_t CH2PCC; /**< timer 2 channel 2 pipeline capture compare */
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reg32_t CH2CC; /**< timer 2 channel 2 capture compare */
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reg32_t CH3EVCFG; /**< timer 2 channel 3 event configuration */
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reg32_t CH3CCFG; /**< timer 2 channel 3 capture configuration */
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reg32_t CH3PCC; /**< timer 2 channel 3 pipeline capture compare */
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reg32_t CH3CC; /**< timer 2 channel 3 capture compare */
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} aux_timer2_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_TIMER2_BASE 0x400C3000 /**< AUX_WUC base address */
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/** @} */
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#define AUX_TIMER2 ((aux_timer2_regs_t *) (AUX_TIMER2_BASE)) /**< AUX_TIMER2 register bank */
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/**
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* AUX_SMPH registers
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*/
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typedef struct {
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reg32_t SMPH0; /**< semaphore 0 */
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reg32_t SMPH1; /**< semaphore 1 */
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reg32_t SMPH2; /**< semaphore 2 */
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reg32_t SMPH3; /**< semaphore 3 */
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reg32_t SMPH4; /**< semaphore 4 */
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reg32_t SMPH5; /**< semaphore 5 */
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reg32_t SMPH6; /**< semaphore 6 */
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reg32_t SMPH7; /**< semaphore 7 */
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reg32_t AUTOTAKE; /**< sticky request for single semaphore */
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} aux_smph_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_SMPH_BASE 0x400C8000 /**< AUX_WUC base address */
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/* @} */
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#define AUX_SMPH ((aux_smph_regs_t *) (AUX_SMPH_BASE)) /**< AUX_SMPH register bank */
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/**
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* AUX_ANAIF registers
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*/
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typedef struct {
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reg32_t __reserved1[4]; /**< meh */
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reg32_t ADCCTL; /**< ADC control */
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reg32_t ADCFIFOSTAT; /**< ADC fifo status */
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reg32_t ADCFIFO; /**< ADC fifo */
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reg32_t ADCTRIG; /**< ADC trigger */
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reg32_t ISRCCTL; /**< current source control */
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reg32_t __reserved2[3]; /**< meh */
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reg32_t DACCTL; /**< DAC control */
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reg32_t LPMBIASCTL; /**< low-power mode bias control */
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reg32_t DACSMPLCTL; /**< DAC sample control */
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reg32_t DACSMPLCFG0; /**< DAC sample configuration 0 */
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reg32_t DACSMPLCFG1; /**< DAC sample configuration 1 */
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reg32_t DACVALUE; /**< DAC value */
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reg32_t DACSTAT; /**< DAC status */
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} aux_anaif_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_ANAIF_BASE 0x400C9000 /**< AUX_WUC base address */
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/** @} */
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#define AUX_ANAIF ((aux_anaif_regs_t *) (AUX_ANAIF_BASE)) /**< AUX_ANAIF register bank */
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/**
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* ADI_4_AUX registers
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*/
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typedef struct {
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reg8_t MUX0; /**< multiplexer 0 */
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reg8_t MUX1; /**< multiplexer 1 */
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reg8_t MUX2; /**< multiplexer 2 */
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reg8_t MUX3; /**< multiplexer 3 */
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reg8_t ISRC; /**< current source */
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reg8_t COMP; /**< comparator */
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reg8_t MUX4; /**< multiplexer 4 */
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reg8_t ADC0; /**< ADC control 0 */
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reg8_t ADC1; /**< ADC control 1 */
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reg8_t ADCREF0; /**< ADC reference 0 */
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reg8_t ADCREF1; /**< ADC reference 1 */
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} adi_4_aux_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define ADI_4_AUX_BASE 0x400CB000 /**< AUX_WUC base address */
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/** @} */
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#define ADI_4_AUX ((adi_4_aux_regs_t *) (ADI_4_AUX_BASE)) /**< ADI_4_AUX register bank */
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#define ADDI_SEM AUX_SMPH->SMPH0 /**< the semamphore used for ADDI */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* CC26X2_CC13X2_AUX_H */
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/** @}*/
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