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https://github.com/RIOT-OS/RIOT.git
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147 lines
3.6 KiB
C
147 lines
3.6 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_ezr32wg
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Override the timer undefined value
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*/
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#define TIMER_UNDEF (0xffffffff)
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/**
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* @brief Override the timer type
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* @{
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*/
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#define HAVE_TIMER_T
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typedef uint32_t tim_t;
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/** @} */
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/**
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* @brief This timer implementation has three available channels
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*/
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#define TIMER_CHANNEL_NUMOF (3)
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/**
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* @brief Starting offset of CPU_ID
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*/
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#define CPUID_ADDR (&DEVINFO->UNIQUEL)
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/**
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* @brief Length of the CPU_ID in octets
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*/
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#define CPUID_LEN (8U)
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/**
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* @brief Define timer configuration values
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*
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* @note The two timers must be adjacent to each other (e.g. TIMER0 and
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* TIMER1, or TIMER2 and TIMER3, etc.).
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*/
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typedef struct {
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TIMER_TypeDef *prescaler; /**< the lower numbered neighboring timer */
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TIMER_TypeDef *timer; /**< the higher numbered timer */
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uint8_t pre_cmu; /**< prescale timer bit in CMU register, the
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* timer bit is deducted from this */
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uint8_t irqn; /**< number of the higher timer IRQ channel */
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} timer_conf_t;
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/**
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* @brief Define a custom type for GPIO pins
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* @{
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*/
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#define HAVE_GPIO_T
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typedef uint32_t gpio_t;
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/** @} */
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/**
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* @brief Definition of a fitting UNDEF value
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*/
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#define GPIO_UNDEF (0xffffffff)
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/**
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* @brief Mandatory function for defining a GPIO pins
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* @{
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*/
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#define GPIO_PIN(x, y) ((x << 4) | y)
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/**
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* @brief Available ports on the SAMD21
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*/
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enum {
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PA = 0, /**< port A */
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PB = 1, /**< port B */
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PC = 2, /**< port C */
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PD = 3, /**< port D */
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PE = 4, /**< port E */
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PF = 5 /**< port F */
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};
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#ifndef DOXYGEN
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/**
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* @brief Override GPIO modes
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* @{
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*/
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#define HAVE_GPIO_MODE_T
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typedef enum {
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GPIO_IN = _GPIO_P_MODEL_MODE0_INPUT, /**< IN */
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GPIO_IN_PD = _GPIO_P_MODEL_MODE0_INPUTPULL, /**< IN with pull-down */
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GPIO_IN_PU = _GPIO_P_MODEL_MODE0_INPUTPULL, /**< IN with pull-up */
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GPIO_OUT = _GPIO_P_MODEL_MODE0_PUSHPULL, /**< OUT (push-pull) */
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GPIO_OD = _GPIO_P_MODEL_MODE0_WIREDAND, /**< OD */
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GPIO_OD_PU = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP /**< OD with pull-up */
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} gpio_mode_t;
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/** @} */
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/**
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* @brief Override active flank configuration values
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* @{
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*/
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_FALLING = 2, /**< emit interrupt on falling flank */
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GPIO_RISING = 1, /**< emit interrupt on rising flank */
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GPIO_BOTH = 3 /**< emit interrupt on both flanks */
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} gpio_flank_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief UART device configuration
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*/
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typedef struct {
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USART_TypeDef *dev; /**< USART device used */
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gpio_t rx_pin; /**< Pin used for RX */
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gpio_t tx_pin; /**< Pin used for TX */
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uint8_t loc; /**< location of USART pins (AF) */
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uint8_t cmu; /**< the device CMU channel */
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uint8_t irq; /**< the devices base IRQ channel */
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} uart_conf_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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