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https://github.com/RIOT-OS/RIOT.git
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154 lines
3.8 KiB
C
154 lines
3.8 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_spark-core
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the spark-core board
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*
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* @author Christian Mehlis <mehlis@inf.fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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**/
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/* high speed clock configuration:
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* 0 := use internal HSI oscillator (always 8MHz)
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* HSE frequency value := use external HSE oscillator with given freq [in Hz]
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* must be 4000000 <= value <= 16000000 */
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#define CLOCK_HSE (8000000U)
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/* low speed clock configuration:
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* 0 := use internal LSI oscillator (~40kHz)
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* 1 := use extern LSE oscillator, always 32.768kHz */
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#define CLOCK_LSE (0)
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/* targeted system clock speed [in Hz], must be <= 72MHz */
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#define CLOCK_CORECLOCK (72000000U)
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/* PLL configuration, set both values to zero to disable PLL usage. The values
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* must be set to satisfy the following equation:
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* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
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* with
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* 1 <= CLOCK_PLL_DIV <= 2
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* 2 <= CLOCK_PLL_MUL <= 17 */
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#define CLOCK_PLL_DIV (1)
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#define CLOCK_PLL_MUL (9)
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/* AHB and APBx bus clock configuration, keep in mind the following constraints:
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* ABP1 <= 36MHz
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*/
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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},
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{
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.dev = TIM3,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.bus = APB1,
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.irqn = TIM3_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_1_ISR isr_tim3
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.bus = APB1,
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.irqn = USART2_IRQn
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}
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};
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#define UART_0_ISR (isr_usart2)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 36000000Hz */
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7, /* -> 140625Hz */
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6, /* -> 281250Hz */
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4, /* -> 1125000Hz */
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2, /* -> 4500000Hz */
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1 /* -> 9000000Hz */
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},
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{ /* for APB2 @ 72000000Hz */
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7, /* -> 281250Hz */
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7, /* -> 281250Hz */
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5, /* -> 1125000Hz */
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3, /* -> 4500000Hz */
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2 /* -> 9000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_B, 17),
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.miso_pin = GPIO_PIN(PORT_B, 16),
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.sclk_pin = GPIO_PIN(PORT_B, 15),
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.cs_pin = GPIO_UNDEF,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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