mirror of
https://github.com/RIOT-OS/RIOT.git
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293 lines
7.7 KiB
C
293 lines
7.7 KiB
C
/*
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* Copyright (C) 2018 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Collection of pre-computed bus pre-scalers for SPI configuration
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef CFG_SPI_DIVTABLE_H
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#define CFG_SPI_DIVTABLE_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name SPI bus divider values for pre-defined peripheral bus clock speeds
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*
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* @note These spi_divtables are generated using
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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#define CFG_SPIDIV_20 \
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{ /* for 20000000Hz */ \
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7, /* -> 78125Hz */ \
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5, /* -> 312500Hz */ \
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3, /* -> 1250000Hz */ \
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1, /* -> 5000000Hz */ \
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0 /* -> 10000000Hz */ \
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},
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#define CFG_SPIDIV_30 \
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{ /* for 30000000Hz */ \
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7, /* -> 117187Hz */ \
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5, /* -> 468750Hz */ \
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4, /* -> 937500Hz */ \
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2, /* -> 3750000Hz */ \
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1 /* -> 7500000Hz */ \
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},
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#define CFG_SPIDIV_32 \
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{ /* for 32000000Hz */ \
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7, /* -> 125000Hz */ \
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5, /* -> 500000Hz */ \
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4, /* -> 1000000Hz */ \
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2, /* -> 4000000Hz */ \
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1 /* -> 8000000Hz */ \
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},
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#define CFG_SPIDIV_36 \
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{ /* for 36000000Hz */ \
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7, /* -> 140625Hz */ \
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6, /* -> 281250Hz */ \
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4, /* -> 1125000Hz */ \
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2, /* -> 4500000Hz */ \
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1 /* -> 9000000Hz */ \
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},
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#define CFG_SPIDIV_40 \
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{ /* for 40000000Hz */ \
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7, /* -> 156250Hz */ \
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6, /* -> 312500Hz */ \
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4, /* -> 1250000Hz */ \
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2, /* -> 5000000Hz */ \
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1 /* -> 10000000Hz */ \
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},
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#define CFG_SPIDIV_42 \
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{ /* for 42000000Hz */ \
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7, /* -> 164062Hz */ \
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6, /* -> 328125Hz */ \
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4, /* -> 1312500Hz */ \
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2, /* -> 5250000Hz */ \
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1 /* -> 10500000Hz */ \
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},
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#define CFG_SPIDIV_45 \
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{ /* for 45000000Hz */ \
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7, /* -> 175781Hz */ \
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6, /* -> 351562Hz */ \
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5, /* -> 703125Hz */ \
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2, /* -> 5625000Hz */ \
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1 /* -> 11250000Hz */ \
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},
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#define CFG_SPIDIV_48 \
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{ /* for 48000000Hz */ \
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7, /* -> 187500Hz */ \
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6, /* -> 375000Hz */ \
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5, /* -> 750000Hz */ \
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2, /* -> 6000000Hz */ \
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1 /* -> 12000000Hz */ \
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},
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#define CFG_SPIDIV_50 \
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{ /* for 50000000Hz */ \
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7, /* -> 195312Hz */ \
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6, /* -> 390625Hz */ \
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5, /* -> 781250Hz */ \
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2, /* -> 6250000Hz */ \
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1 /* -> 12500000Hz */ \
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},
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#define CFG_SPIDIV_54 \
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{ /* for 54000000Hz */ \
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7, /* -> 210937Hz */ \
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6, /* -> 421875Hz */ \
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5, /* -> 843750Hz */ \
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3, /* -> 3375000Hz */ \
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2 /* -> 6750000Hz */ \
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},
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#define CFG_SPIDIV_60 \
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{ /* for 60000000Hz */ \
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7, /* -> 234375Hz */ \
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6, /* -> 468750Hz */ \
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5, /* -> 937500Hz */ \
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3, /* -> 3750000Hz */ \
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2 /* -> 7500000Hz */ \
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},
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#define CFG_SPIDIV_64 \
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{ /* for 64000000Hz */ \
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7, /* -> 250000Hz */ \
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6, /* -> 500000Hz */ \
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5, /* -> 1000000Hz */ \
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3, /* -> 4000000Hz */ \
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2 /* -> 8000000Hz */ \
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},
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#define CFG_SPIDIV_72 \
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{ /* for 72000000Hz */ \
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7, /* -> 281250Hz */ \
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7, /* -> 281250Hz */ \
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5, /* -> 1125000Hz */ \
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3, /* -> 4500000Hz */ \
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2 /* -> 9000000Hz */ \
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},
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#define CFG_SPIDIV_84 \
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{ /* for 84000000Hz */ \
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7, /* -> 328125Hz */ \
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7, /* -> 328125Hz */ \
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5, /* -> 1312500Hz */ \
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3, /* -> 5250000Hz */ \
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2 /* -> 10500000Hz */ \
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},
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#define CFG_SPIDIV_90 \
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{ /* for 90000000Hz */ \
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7, /* -> 351562Hz */ \
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7, /* -> 351562Hz */ \
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6, /* -> 703125Hz */ \
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3, /* -> 5625000Hz */ \
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2 /* -> 11250000Hz */ \
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},
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#define CFG_SPIDIV_96 \
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{ /* for 96000000Hz */ \
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7, /* -> 375000Hz */ \
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7, /* -> 375000Hz */ \
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6, /* -> 750000Hz */ \
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3, /* -> 6000000Hz */ \
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2 /* -> 12000000Hz */ \
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},
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#define CFG_SPIDIV_100 \
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{ /* for 100000000Hz */ \
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7, /* -> 390625Hz */ \
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7, /* -> 390625Hz */ \
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6, /* -> 781250Hz */ \
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3, /* -> 6250000Hz */ \
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2 /* -> 12500000Hz */ \
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},
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#define CFG_SPIDIV_108 \
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{ /* for 108000000Hz */ \
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7, /* -> 421875Hz */ \
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7, /* -> 421875Hz */ \
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6, /* -> 843750Hz */ \
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4, /* -> 3375000Hz */ \
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3 /* -> 6750000Hz */ \
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},
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/** @} */
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/**
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* @name SPI clock divisors
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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*
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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#if (CLOCK_APB1 == 20000000)
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CFG_SPIDIV_20
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#elif (CLOCK_APB1 == 30000000)
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CFG_SPIDIV_30
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#elif (CLOCK_APB1 == 32000000)
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CFG_SPIDIV_32
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#elif (CLOCK_APB1 == 36000000)
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CFG_SPIDIV_36
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#elif (CLOCK_APB1 == 40000000)
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CFG_SPIDIV_40
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#elif (CLOCK_APB1 == 42000000)
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CFG_SPIDIV_42
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#elif (CLOCK_APB1 == 45000000)
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CFG_SPIDIV_45
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#elif (CLOCK_APB1 == 48000000)
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CFG_SPIDIV_48
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#elif (CLOCK_APB1 == 50000000)
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CFG_SPIDIV_50
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#elif (CLOCK_APB1 == 54000000)
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CFG_SPIDIV_54
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#elif (CLOCK_APB1 == 72000000)
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CFG_SPIDIV_72
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#elif (CLOCK_APB1 == 60000000)
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CFG_SPIDIV_60
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#elif (CLOCK_APB1 == 64000000)
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CFG_SPIDIV_64
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#elif (CLOCK_APB1 == 84000000)
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CFG_SPIDIV_84
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#elif (CLOCK_APB1 == 90000000)
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CFG_SPIDIV_90
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#elif (CLOCK_APB1 == 96000000)
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CFG_SPIDIV_96
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#elif (CLOCK_APB1 == 100000000)
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CFG_SPIDIV_100
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#elif (CLOCK_APB1 == 108000000)
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CFG_SPIDIV_108
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#else
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#error "CFG_SPI_DIVTABLE: no prescalers for selected APB1 bus clock defined"
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#endif
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#if (CLOCK_APB2 == 20000000)
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CFG_SPIDIV_20
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#elif (CLOCK_APB2 == 30000000)
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CFG_SPIDIV_30
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#elif (CLOCK_APB2 == 32000000)
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CFG_SPIDIV_32
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#elif (CLOCK_APB2 == 36000000)
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CFG_SPIDIV_36
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#elif (CLOCK_APB2 == 40000000)
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CFG_SPIDIV_40
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#elif (CLOCK_APB2 == 42000000)
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CFG_SPIDIV_42
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#elif (CLOCK_APB2 == 45000000)
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CFG_SPIDIV_45
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#elif (CLOCK_APB2 == 48000000)
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CFG_SPIDIV_48
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#elif (CLOCK_APB2 == 50000000)
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CFG_SPIDIV_50
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#elif (CLOCK_APB2 == 54000000)
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CFG_SPIDIV_54
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#elif (CLOCK_APB2 == 72000000)
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CFG_SPIDIV_72
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#elif (CLOCK_APB2 == 60000000)
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CFG_SPIDIV_60
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#elif (CLOCK_APB2 == 64000000)
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CFG_SPIDIV_64
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#elif (CLOCK_APB2 == 84000000)
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CFG_SPIDIV_84
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#elif (CLOCK_APB2 == 90000000)
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CFG_SPIDIV_90
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#elif (CLOCK_APB2 == 96000000)
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CFG_SPIDIV_96
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#elif (CLOCK_APB2 == 100000000)
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CFG_SPIDIV_100
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#elif (CLOCK_APB2 == 108000000)
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CFG_SPIDIV_108
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#else
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#error "CFG_SPI_DIVTABLE: no prescalers for selected APB2 bus clock defined"
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#endif
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* CFG_SPI_DIVTABLE_H */
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/** @} */
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