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https://github.com/RIOT-OS/RIOT.git
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064c799e57
- periph/eeprom.c - periph/wdt.c - periph/gpio_ll_irq.c removed unsupported cpuid and dpgpin feature for atmega8 cpu familly pkg/qdsa: bump the commit hash bump the commit hash after RIOT-OS/qDSA#4 was merged
184 lines
4.0 KiB
C
184 lines
4.0 KiB
C
/*
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* Copyright (C) 2015 HAW Hamburg
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* 2016 INRIA
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* 2022 Otto-von-Guericke-Universität Magdeburg
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* 2023 Gerson Fernando Budke
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* 2023 Hugues Larrive
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_atmega_common
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* @ingroup drivers_periph_gpio_ll_irq
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* @{
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*
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* @file
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* @brief IRQ implementation of the GPIO Low-Level API for ATmega
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*
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* @author René Herthel <rene-herthel@outlook.de>
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* @author Francisco Acosta <francisco.acosta@inria.fr>
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* @author Laurent Navet <laurent.navet@gmail.com>
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* @author Robert Hartung <hartung@ibr.cs.tu-bs.de>
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* @author Torben Petersen <petersen@ibr.cs.tu-bs.de>
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* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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* @author Hugues Larrive <hugues.larrive@pm.me>
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*
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* @}
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*/
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#include <avr/interrupt.h>
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#include <errno.h>
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#include "cpu.h"
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#include "irq.h"
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#include "periph/gpio_ll_irq.h"
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#include "periph_conf.h"
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#include "periph_cpu.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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struct isr_ctx {
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gpio_ll_cb_t cb;
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void *arg;
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};
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static struct isr_ctx isr_ctx[GPIO_EXT_INT_NUMOF];
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static void clear_pending_irqs(uint8_t exti)
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{
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#if defined(EIFR)
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EIFR |= 1 << exti;
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#elif defined(GIFR)
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GIFR |= 1 << (INTF0 + exti);
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#else
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# error "No support for AVR with neither EIFR nor GIFR"
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#endif
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}
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void gpio_ll_irq_mask(gpio_port_t port, uint8_t pin)
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{
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uint8_t exti = atmega_pin2exti(GPIO_PORT_NUM(port), pin);
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#if defined(EIMSK)
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EIMSK &= ~(1 << exti);
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#elif defined(GICR)
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GICR &= ~(1 << (INT0 + exti));
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#endif
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}
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void gpio_ll_irq_unmask(gpio_port_t port, uint8_t pin)
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{
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uint8_t exti = atmega_pin2exti(GPIO_PORT_NUM(port), pin);
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#if defined(EIMSK)
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EIMSK |= 1 << exti;
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#elif defined(GICR)
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GICR |= 1 << (INT0 + exti);
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#endif
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}
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void gpio_ll_irq_unmask_and_clear(gpio_port_t port, uint8_t pin)
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{
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uint8_t exti = atmega_pin2exti(GPIO_PORT_NUM(port), pin);
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clear_pending_irqs(exti);
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#if defined(EIMSK)
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EIMSK |= 1 << exti;
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#elif defined(GICR)
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GICR |= 1 << (INT0 + exti);
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#endif
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}
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static void set_trigger(uint8_t exti, gpio_irq_trig_t trig)
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{
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exti <<= 1;
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#if defined(EICRA)
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volatile uint8_t *eicr = &EICRA;
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#elif defined(MCUCR)
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volatile uint8_t *eicr = &MCUCR;
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#endif
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#ifdef EICRB
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if (exti >= 8) {
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eicr = & EICRB;
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exti -= 8;
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}
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#endif
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/* being a bit more verbose here to avoid two read-modify-write cycles,
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* as the compiler won't optimize access to volatile memory */
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uint8_t tmp = *eicr;
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tmp &= ~(0x3 << exti);
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tmp |= trig << exti;
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*eicr = tmp;
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}
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int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig,
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gpio_ll_cb_t cb, void *arg)
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{
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int port_num = GPIO_PORT_NUM(port);
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assert((trig != GPIO_TRIGGER_LEVEL_HIGH) && cb);
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if (!atmega_has_pin_exti(port_num, pin)) {
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return -ENOTSUP;
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}
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uint8_t exti = atmega_pin2exti(port_num, pin);
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unsigned irq_state = irq_disable();
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/* set callback */
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isr_ctx[exti].cb = cb;
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isr_ctx[exti].arg = arg;
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/* setup IRQ */
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set_trigger(exti, trig);
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clear_pending_irqs(exti);
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#if defined(EIMSK)
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EIMSK |= 1 << exti;
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#elif defined(GICR)
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GICR |= 1 << (INT0 + exti);
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#endif
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irq_restore(irq_state);
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return 0;
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}
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static void isr_exti(uint8_t exti)
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{
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isr_ctx[exti].cb(isr_ctx[exti].arg);
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}
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#ifdef INT0_vect
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AVR8_ISR(INT0_vect, isr_exti, 0);
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#endif
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#ifdef INT1_vect
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AVR8_ISR(INT1_vect, isr_exti, 1);
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#endif
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#ifdef INT2_vect
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AVR8_ISR(INT2_vect, isr_exti, 2);
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#endif
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#ifdef INT3_vect
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AVR8_ISR(INT3_vect, isr_exti, 3);
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#endif
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#ifdef INT4_vect
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AVR8_ISR(INT4_vect, isr_exti, 4);
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#endif
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#ifdef INT5_vect
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AVR8_ISR(INT5_vect, isr_exti, 5);
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#endif
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#ifdef INT6_vect
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AVR8_ISR(INT6_vect, isr_exti, 6);
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#endif
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#ifdef INT7_vect
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AVR8_ISR(INT7_vect, isr_exti, 7);
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#endif
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