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87 lines
4.6 KiB
C
87 lines
4.6 KiB
C
/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Interrupt vector definitions for STM32G0
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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* @}
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*/
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#include "vectors_cortexm.h"
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* STM32G0 specific interrupt vectors */
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WEAK_DEFAULT void isr_adc1(void);
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WEAK_DEFAULT void isr_dma1_channel1(void);
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WEAK_DEFAULT void isr_dma1_channel2_3(void);
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WEAK_DEFAULT void isr_dma1_ch4_7_dmamux1_ovr(void);
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WEAK_DEFAULT void isr_exti(void);
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WEAK_DEFAULT void isr_flash(void);
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WEAK_DEFAULT void isr_i2c1(void);
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WEAK_DEFAULT void isr_i2c2(void);
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WEAK_DEFAULT void isr_rcc(void);
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WEAK_DEFAULT void isr_rtc_tamp(void);
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WEAK_DEFAULT void isr_spi1(void);
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WEAK_DEFAULT void isr_spi2(void);
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WEAK_DEFAULT void isr_tim1_brk_up_trg_com(void);
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WEAK_DEFAULT void isr_tim1_cc(void);
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WEAK_DEFAULT void isr_tim3(void);
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WEAK_DEFAULT void isr_tim6(void);
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WEAK_DEFAULT void isr_tim7(void);
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WEAK_DEFAULT void isr_tim14(void);
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WEAK_DEFAULT void isr_tim15(void);
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WEAK_DEFAULT void isr_tim16(void);
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WEAK_DEFAULT void isr_tim17(void);
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WEAK_DEFAULT void isr_usart1(void);
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WEAK_DEFAULT void isr_usart2(void);
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WEAK_DEFAULT void isr_usart3_4(void);
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WEAK_DEFAULT void isr_wwdg(void);
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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/* shared vectors for all family members */
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[WWDG_IRQn ] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */
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[RTC_TAMP_IRQn ] = isr_rtc_tamp, /* [ 2] RTC interrupt through the EXTI line 19 & 21 */
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[FLASH_IRQn ] = isr_flash, /* [ 3] FLASH global Interrupt */
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[RCC_IRQn ] = isr_rcc, /* [ 4] RCC global Interrupt */
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[EXTI0_1_IRQn ] = isr_exti, /* [ 5] EXTI 0 and 1 Interrupts */
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[EXTI2_3_IRQn ] = isr_exti, /* [ 6] EXTI 2 and 3 Interrupts */
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[EXTI4_15_IRQn ] = isr_exti, /* [ 7] EXTI 4 to 15 Interrupts */
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[DMA1_Channel1_IRQn ] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */
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[DMA1_Channel2_3_IRQn ] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupts */
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[DMA1_Ch4_7_DMAMUX1_OVR_IRQn ] = isr_dma1_ch4_7_dmamux1_ovr, /* [11] DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */
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[ADC1_IRQn ] = isr_adc1, /* [12] ADC1 Interrupts */
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[TIM1_BRK_UP_TRG_COM_IRQn ] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupts */
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[TIM1_CC_IRQn ] = isr_tim1_cc, /* [14] TIM1 Capture Compare Interrupt */
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[TIM3_IRQn ] = isr_tim3, /* [16] TIM3 global Interrupt */
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[TIM6_IRQn ] = isr_tim6, /* [17] TIM6 global Interrupts */
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[TIM7_IRQn ] = isr_tim7, /* [18] TIM7 global Interrupt */
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[TIM14_IRQn ] = isr_tim14, /* [19] TIM14 global Interrupt */
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[TIM15_IRQn ] = isr_tim15, /* [20] TIM15 global Interrupt */
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[TIM16_IRQn ] = isr_tim16, /* [21] TIM16 global Interrupt */
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[TIM17_IRQn ] = isr_tim17, /* [22] TIM17 global Interrupt */
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[I2C1_IRQn ] = isr_i2c1, /* [23] I2C1 Interrupt (combined with EXTI 23) */
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[I2C2_IRQn ] = isr_i2c2, /* [24] I2C2 Interrupt */
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[SPI1_IRQn ] = isr_spi1, /* [25] SPI1/I2S1 Interrupt */
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[SPI2_IRQn ] = isr_spi2, /* [26] SPI2 Interrupt */
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[USART1_IRQn ] = isr_usart1, /* [27] USART1 Interrupt */
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[USART2_IRQn ] = isr_usart2, /* [28] USART2 Interrupt */
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[USART3_4_IRQn ] = isr_usart3_4, /* [29] USART3, USART4 globlal Interrupts */
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};
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