mirror of
https://github.com/RIOT-OS/RIOT.git
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278 lines
8.1 KiB
C
278 lines
8.1 KiB
C
/*
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* Copyright (C) 2017 SKF AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup drivers_kw41zrf
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* @{
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* @file
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* @brief get/set functionality of kw41zrf driver
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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* @}
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include "log.h"
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#include "cpu.h"
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#include "byteorder.h"
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#include "kw41zrf.h"
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#include "kw41zrf_intern.h"
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#include "kw41zrf_getset.h"
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#include "vendor/MKW41Z4.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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#define KW41ZRF_NUM_CHANNEL (KW41ZRF_MAX_CHANNEL - KW41ZRF_MIN_CHANNEL + 1)
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/* Lookup table for PA_PWR register */
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/* Source: KW41Z data sheet, 5.3 Transmit and PLL Feature Summary,
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* Table 8. Transmit Output Power as a function of PA_POWER[5:0] */
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static const uint8_t tx_power_dbm_to_pa_pwr[29] = {
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4, 4, 4, 4, /* -19:-16 dBm */
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6, 6, /* -15:-14 dBm */
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8, 8, /* -13:-12 dBm */
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10, 10, /* -11:-10 dBm */
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12, /* -9 dBm */
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14, /* -8 dBm */
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16, /* -7 dBm */
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18, /* -6 dBm */
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20, /* -5 dBm */
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22, /* -4 dBm */
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26, /* -3 dBm */
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28, /* -2 dBm */
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34, /* -1 dBm */
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38, /* 0 dBm */
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42, /* 1 dBm */
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48, /* 2 dBm */
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56, /* 3 dBm */
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62, /* 4 dBm */
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};
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void kw41zrf_set_tx_power(kw41zrf_t *dev, int16_t txpower_dbm)
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{
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if (txpower_dbm < KW41ZRF_OUTPUT_POWER_MIN) {
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txpower_dbm = KW41ZRF_OUTPUT_POWER_MIN;
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}
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else if (txpower_dbm > KW41ZRF_OUTPUT_POWER_MAX) {
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txpower_dbm = KW41ZRF_OUTPUT_POWER_MAX;
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}
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ZLL->PA_PWR = tx_power_dbm_to_pa_pwr[txpower_dbm - KW41ZRF_OUTPUT_POWER_MIN];
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DEBUG("[kw41zrf] set txpower to: %d\n", txpower_dbm);
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dev->tx_power = txpower_dbm;
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}
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int16_t kw41zrf_get_txpower(kw41zrf_t *dev)
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{
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return dev->tx_power;
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}
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uint8_t kw41zrf_get_channel(kw41zrf_t *dev)
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{
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(void) dev;
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return (ZLL->CHANNEL_NUM0 & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK)
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>> ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT;
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}
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uint16_t kw41zrf_get_pan(kw41zrf_t *dev)
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{
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(void) dev;
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return (ZLL->MACSHORTADDRS0 & ZLL_MACSHORTADDRS0_MACPANID0_MASK)
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>> ZLL_MACSHORTADDRS0_MACPANID0_SHIFT;
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}
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int kw41zrf_set_channel(kw41zrf_t *dev, uint8_t channel)
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{
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(void) dev;
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if (channel < KW41ZRF_MIN_CHANNEL || channel > KW41ZRF_MAX_CHANNEL) {
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LOG_ERROR("[kw41zrf] Invalid channel %u\n", channel);
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return -EINVAL;
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}
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ZLL->CHANNEL_NUM0 = channel;
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DEBUG("[kw41zrf] set channel to %u\n", channel);
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return 0;
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}
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void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan)
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{
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(void) dev;
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ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0
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& ~ZLL_MACSHORTADDRS0_MACPANID0_MASK) |
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ZLL_MACSHORTADDRS0_MACPANID0(pan);
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DEBUG("[kw41zrf] set pan to: 0x%x\n", pan);
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}
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void kw41zrf_set_addr_short(kw41zrf_t *dev, const network_uint16_t *addr)
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{
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(void) dev;
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/* radio hardware stores this in little endian */
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ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0
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& ~ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) |
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ZLL_MACSHORTADDRS0_MACSHORTADDRS0(byteorder_swaps(
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addr->u16));
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}
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void kw41zrf_set_addr_long(kw41zrf_t *dev, const eui64_t *addr)
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{
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(void) dev;
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ZLL->MACLONGADDRS0_LSB = addr->uint32[0].u32;
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ZLL->MACLONGADDRS0_MSB = addr->uint32[1].u32;
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}
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void kw41zrf_get_addr_short(kw41zrf_t *dev, network_uint16_t *addr)
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{
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(void) dev;
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addr->u16 = (ZLL->MACSHORTADDRS0 & ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) >>
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ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT;
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/* radio hardware stores this in little endian */
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addr->u16 = byteorder_swaps(addr->u16);
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}
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void kw41zrf_get_addr_long(kw41zrf_t *dev, eui64_t *addr)
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{
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(void) dev;
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addr->uint32[0] = (network_uint32_t)ZLL->MACLONGADDRS0_LSB;
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addr->uint32[1] = (network_uint32_t)ZLL->MACLONGADDRS0_MSB;
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}
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int8_t kw41zrf_get_cca_threshold(kw41zrf_t *dev)
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{
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(void) dev;
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uint8_t tmp = (ZLL->CCA_LQI_CTRL & ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) >>
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ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT;
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return (int8_t)tmp;
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}
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void kw41zrf_set_cca_threshold(kw41zrf_t *dev, int8_t value)
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{
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(void) dev;
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ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) |
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ZLL_CCA_LQI_CTRL_CCA1_THRESH(value);
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}
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void kw41zrf_set_cca_mode(kw41zrf_t *dev, uint8_t mode)
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{
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(void) dev;
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ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_CCATYPE_MASK) |
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ZLL_PHY_CTRL_CCATYPE(mode);
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}
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uint8_t kw41zrf_get_cca_mode(kw41zrf_t *dev)
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{
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(void) dev;
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return (ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCATYPE_MASK) >> ZLL_PHY_CTRL_CCATYPE_SHIFT;
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}
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int8_t kw41zrf_get_ed_level(kw41zrf_t *dev)
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{
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(void) dev;
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return (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK)
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>> ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT;
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}
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void kw41zrf_set_option(kw41zrf_t *dev, uint8_t option, uint8_t state)
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{
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DEBUG("[kw41zrf] set option 0x%04x to %x\n", option, state);
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if (kw41zrf_is_dsm()) {
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/* Transceiver is sleeping */
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switch (option) {
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/* Modifying these options require that the transceiver is not in
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* deep sleep mode */
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case KW41ZRF_OPT_CSMA:
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case KW41ZRF_OPT_PROMISCUOUS:
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case KW41ZRF_OPT_AUTOACK:
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case KW41ZRF_OPT_ACK_PENDING:
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LOG_ERROR("[kw41zrf] Attempt to modify option %04x while radio is sleeping\n",
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(unsigned) option);
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assert(0);
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return;
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default:
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break;
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}
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}
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/* set option field */
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if (state) {
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dev->flags |= option;
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/* trigger option specific actions */
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switch (option) {
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case KW41ZRF_OPT_CSMA:
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DEBUG("[kw41zrf] enable: CSMA\n");
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bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_CCABFRTX_SHIFT);
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break;
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case KW41ZRF_OPT_PROMISCUOUS:
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DEBUG("[kw41zrf] enable: PROMISCUOUS\n");
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/* enable promiscuous mode */
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bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_PROMISCUOUS_SHIFT);
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/* auto ACK is always disabled in promiscuous mode by the hardware */
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break;
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case KW41ZRF_OPT_AUTOACK:
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DEBUG("[kw41zrf] enable: AUTOACK\n");
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bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_AUTOACK_SHIFT);
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break;
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case KW41ZRF_OPT_ACK_PENDING:
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DEBUG("[kw41zrf] enable: PENDING_BIT\n");
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bit_set32(&ZLL->SAM_TABLE, ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT);
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break;
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default:
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/* do nothing */
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break;
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}
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}
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else {
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dev->flags &= ~(option);
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/* trigger option specific actions */
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switch (option) {
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case KW41ZRF_OPT_CSMA:
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DEBUG("[kw41zrf] disable: CSMA\n");
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bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_CCABFRTX_SHIFT);
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break;
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case KW41ZRF_OPT_PROMISCUOUS:
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DEBUG("[kw41zrf] disable: PROMISCUOUS\n");
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/* disable promiscuous mode */
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bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_PROMISCUOUS_SHIFT);
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break;
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case KW41ZRF_OPT_AUTOACK:
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DEBUG("[kw41zrf] disable: AUTOACK\n");
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bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_AUTOACK_SHIFT);
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break;
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case KW41ZRF_OPT_ACK_PENDING:
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DEBUG("[kw41zrf] disable: PENDING_BIT\n");
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bit_clear32(&ZLL->SAM_TABLE, ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT);
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break;
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default:
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/* do nothing */
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break;
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}
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}
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}
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void kw41zrf_set_rx_watermark(kw41zrf_t *dev, uint8_t value)
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{
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(void) dev;
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ZLL->RX_WTR_MARK = ZLL_RX_WTR_MARK_RX_WTR_MARK(value);
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}
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