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https://github.com/RIOT-OS/RIOT.git
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377b5b321c
The default timer configuration has been changed so that `TIMER0` and `TIMER1` are always timer devices. `TIMER2` can only be used as timer device if it is not used for PWM devices. `TIMER3` and `TIMER4` are only available as timer devices if they are supported by the CPU model and not used for PWM devices.
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
/*
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* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
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* 2023 Gunar Schorcht <gunar@schorcht.net>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_gd32v
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* @{
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*
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* @file
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* @brief Default timer configuration for GD32VF103 boards
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*
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* @author Koen Zandberg <koen@bergzand.net>
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef CFG_TIMER_DEFAULT_H
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#define CFG_TIMER_DEFAULT_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Timer configuration
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*
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* All GD32VF103xx variants have at least one advanced timer TIMER0 and two
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* general timers TIMER1 and TIMER2. GD32VF10x8 and GD32VF10xB have two
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* additional general timers TIMER3 and TIMER4.
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*
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIMER0,
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.max = 0x0000ffff,
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.rcu_mask = RCU_APB2EN_TIMER0EN_Msk,
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.bus = APB2,
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.irqn = TIMER0_Channel_IRQn
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},
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{
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.dev = TIMER1,
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.max = 0x0000ffff,
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.rcu_mask = RCU_APB1EN_TIMER1EN_Msk,
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.bus = APB1,
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.irqn = TIMER1_IRQn
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},
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#if !defined(MODULE_PERIPH_PM)
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{
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.dev = TIMER2,
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.max = 0x0000ffff,
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.rcu_mask = RCU_APB1EN_TIMER2EN_Msk,
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.bus = APB1,
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.irqn = TIMER2_IRQn
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},
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#if defined(CPU_MODEL_GD32VF103C8T6) || defined(CPU_MODEL_GD32VF103CBT6) || \
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defined(CPU_MODEL_GD32VF103R8T6) || defined(CPU_MODEL_GD32VF103RBT6) || \
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defined(CPU_MODEL_GD32VF103T8U6) || defined(CPU_MODEL_GD32VF103TBU6) || \
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defined(CPU_MODEL_GD32VF103V8T6) || defined(CPU_MODEL_GD32VF103VBT6)
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{
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.dev = TIMER3,
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.max = 0x0000ffff,
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.rcu_mask = RCU_APB1EN_TIMER3EN_Msk,
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.bus = APB1,
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.irqn = TIMER3_IRQn
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},
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{
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.dev = TIMER4,
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.max = 0x0000ffff,
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.rcu_mask = RCU_APB1EN_TIMER4EN_Msk,
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.bus = APB1,
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.irqn = TIMER4_IRQn
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}
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#endif
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#endif /* !defined(MODULE_PERIPH_PWM) */
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};
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#define TIMER_0_IRQN TIMER0_Channel_IRQn
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#define TIMER_1_IRQN TIMER1_IRQn
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#if !defined(MODULE_PERIPH_PWM)
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#define TIMER_2_IRQN TIMER2_IRQn
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#if defined(CPU_MODEL_GD32VF103C8T6) || defined(CPU_MODEL_GD32VF103CBT6) || \
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defined(CPU_MODEL_GD32VF103R8T6) || defined(CPU_MODEL_GD32VF103RBT6) || \
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defined(CPU_MODEL_GD32VF103T8U6) || defined(CPU_MODEL_GD32VF103TBU6) || \
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defined(CPU_MODEL_GD32VF103V8T6) || defined(CPU_MODEL_GD32VF103VBT6)
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#define TIMER_3_IRQN TIMER3_IRQn
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#define TIMER_4_IRQN TIMER4_IRQn
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#endif
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#endif /* !defined(MODULE_PERIPH_PWM) */
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CFG_TIMER_DEFAULT_H */
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/** @} */
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