mirror of
https://github.com/RIOT-OS/RIOT.git
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e7fbaf3815
- removed the __attribute__((naked)) from ISRs - removed ISR_ENTER() and ISR_EXIT() macros Rationale: Cortex-Mx MCUs save registers R0-R4 automatically on calling ISRs. The naked attribute tells the compiler not to save any other registers. This is fine, as long as the code in the ISR is not nested. If nested, it will use also R4 and R5, which will then lead to currupted registers on exit of the ISR. Removing the naked will fix this.
332 lines
6.8 KiB
C
332 lines
6.8 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32f4
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* @{
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*
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* @file
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* @brief Low-level timer driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include <stdlib.h>
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#include "cpu.h"
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#include "board.h"
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#include "sched.h"
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#include "thread.h"
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#include "periph_conf.h"
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#include "periph/timer.h"
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/** Unified IRQ handler for all timers */
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static inline void irq_handler(tim_t timer, TIM_TypeDef *dev);
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/** Type for timer state */
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typedef struct {
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void (*cb)(int);
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} timer_conf_t;
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/** Timer state memory */
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timer_conf_t config[TIMER_NUMOF];
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int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
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{
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TIM_TypeDef *timer;
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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/* enable timer peripheral clock */
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TIMER_0_CLKEN();
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/* set timer's IRQ priority */
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NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO);
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/* select timer */
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timer = TIMER_0_DEV;
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timer->PSC = TIMER_0_PRESCALER * ticks_per_us;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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/* enable timer peripheral clock */
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TIMER_1_CLKEN();
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/* set timer's IRQ priority */
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NVIC_SetPriority(TIMER_1_IRQ_CHAN, TIMER_IRQ_PRIO);
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/* select timer */
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timer = TIMER_1_DEV;
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timer->PSC = TIMER_0_PRESCALER * ticks_per_us;
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return -1;
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}
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/* set callback function */
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config[dev].cb = callback;
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/* set timer to run in counter mode */
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timer->CR1 = 0;
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timer->CR2 = 0;
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/* set auto-reload and prescaler values and load new values */
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timer->EGR |= TIM_EGR_UG;
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/* enable the timer's interrupt */
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timer_irq_enable(dev);
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/* start the timer */
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timer_start(dev);
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return 0;
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}
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int timer_set(tim_t dev, int channel, unsigned int timeout)
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{
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int now = timer_read(dev);
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return timer_set_absolute(dev, channel, now + timeout - 1);
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}
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int timer_set_absolute(tim_t dev, int channel, unsigned int value)
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{
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TIM_TypeDef *timer;
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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timer = TIMER_0_DEV;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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timer = TIMER_1_DEV;
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return -1;
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}
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switch (channel) {
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case 0:
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timer->CCR1 = value;
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timer->SR &= ~TIM_SR_CC1IF;
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timer->DIER |= TIM_DIER_CC1IE;
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break;
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case 1:
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timer->CCR2 = value;
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timer->SR &= ~TIM_SR_CC2IF;
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timer->DIER |= TIM_DIER_CC2IE;
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break;
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case 2:
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timer->CCR3 = value;
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timer->SR &= ~TIM_SR_CC3IF;
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timer->DIER |= TIM_DIER_CC3IE;
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break;
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case 3:
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timer->CCR4 = value;
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timer->SR &= ~TIM_SR_CC4IF;
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timer->DIER |= TIM_DIER_CC4IE;
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break;
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default:
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return -1;
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}
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return 0;
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}
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int timer_clear(tim_t dev, int channel)
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{
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TIM_TypeDef *timer;
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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timer = TIMER_0_DEV;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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timer = TIMER_1_DEV;
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return -1;
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}
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switch (channel) {
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case 0:
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timer->DIER &= ~TIM_DIER_CC1IE;
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break;
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case 1:
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timer->DIER &= ~TIM_DIER_CC2IE;
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break;
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case 2:
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timer->DIER &= ~TIM_DIER_CC3IE;
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break;
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case 3:
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timer->DIER &= ~TIM_DIER_CC4IE;
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break;
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default:
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return -1;
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}
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return 0;
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}
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unsigned int timer_read(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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return TIMER_0_DEV->CNT;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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return TIMER_1_DEV->CNT;
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return 0;
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}
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}
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void timer_start(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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TIMER_0_DEV->CR1 |= TIM_CR1_CEN;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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TIMER_1_DEV->CR1 |= TIM_CR1_CEN;
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break;
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#endif
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case TIMER_UNDEFINED:
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break;
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}
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}
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void timer_stop(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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TIMER_0_DEV->CR1 &= ~TIM_CR1_CEN;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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TIMER_1_DEV->CR1 &= ~TIM_CR1_CEN;
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break;
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#endif
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case TIMER_UNDEFINED:
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break;
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}
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}
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void timer_irq_enable(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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NVIC_EnableIRQ(TIMER_0_IRQ_CHAN);
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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NVIC_EnableIRQ(TIMER_1_IRQ_CHAN);
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break;
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#endif
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case TIMER_UNDEFINED:
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break;
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}
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}
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void timer_irq_disable(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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NVIC_DisableIRQ(TIMER_0_IRQ_CHAN);
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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NVIC_DisableIRQ(TIMER_1_IRQ_CHAN);
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break;
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#endif
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case TIMER_UNDEFINED:
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break;
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}
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}
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void timer_reset(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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TIMER_0_DEV->CNT = 0;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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TIMER_1_DEV->CNT = 0;
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break;
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#endif
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case TIMER_UNDEFINED:
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break;
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}
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}
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void TIMER_0_ISR(void)
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{
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irq_handler(TIMER_0, TIMER_0_DEV);
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}
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void TIMER_1_ISR(void)
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{
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irq_handler(TIMER_1, TIMER_1_DEV);
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}
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static inline void irq_handler(tim_t timer, TIM_TypeDef *dev)
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{
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if (dev->SR & TIM_SR_CC1IF) {
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dev->DIER &= ~TIM_DIER_CC1IE;
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dev->SR &= ~TIM_SR_CC1IF;
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config[timer].cb(0);
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}
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else if (dev->SR & TIM_SR_CC2IF) {
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dev->DIER &= ~TIM_DIER_CC2IE;
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dev->SR &= ~TIM_SR_CC2IF;
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config[timer].cb(1);
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}
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else if (dev->SR & TIM_SR_CC3IF) {
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dev->DIER &= ~TIM_DIER_CC3IE;
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dev->SR &= ~TIM_SR_CC3IF;
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config[timer].cb(2);
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}
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else if (dev->SR & TIM_SR_CC4IF) {
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dev->DIER &= ~TIM_DIER_CC4IE;
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dev->SR &= ~TIM_SR_CC4IF;
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config[timer].cb(3);
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}
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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