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b9744f698f
Before this change, if one tried to build a Cortex-M0+ target that had an MPU, compilation would fail due to missing 'SCB_SHCSR_MEMFAULTENA_Msk' in SCB structure. Cortex-M0+ is a ARMv6-M arch (unlike most other targets that have MPU support). ARMv6-M has more limited support for fault conditions, see ARMv6-M Architecture Reference Manual, D3.6.2. |
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.. | ||
include | ||
ldscripts | ||
periph | ||
cortexm_init.c | ||
irq_arch.c | ||
Makefile | ||
Makefile.features | ||
Makefile.include | ||
mpu.c | ||
panic.c | ||
thread_arch.c | ||
vectors_cortexm.c |