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85 lines
3.4 KiB
C
85 lines
3.4 KiB
C
/*
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* Copyright (C) 2018 Koen Zandberg
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* 2021 Francisco Molina
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_lcd
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* @{
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*
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* @file
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* @brief Device driver implementation for the lcd display controller
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*
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* @author Koen Zandberg <koen@bergzand.net>
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* @author Francisco Molina <francois-xavier.molina@inria.fr>
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*
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* @}
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*/
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#ifndef LCD_INTERNAL_H
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#define LCD_INTERNAL_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name LCD commands
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*
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* Not exhaustive, please extend when required
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* @{
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*/
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#define LCD_CMD_SWRESET 0x01 /**< Software reset */
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#define LCD_CMD_RDDIDIF 0x04 /**< Read display ID */
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#define LCD_CMD_RDDST 0x09 /**< Read display status */
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#define LCD_CMD_SLPIN 0x10 /**< Enter sleep mode */
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#define LCD_CMD_SLPOUT 0x11 /**< Sleep out */
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#define LCD_CMD_NORON 0x13 /**< Normal display mode on */
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#define LCD_CMD_DINVOFF 0x20 /**< Display inversion off */
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#define LCD_CMD_DINVON 0x21 /**< Display inversion on */
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#define LCD_CMD_GAMSET 0x26 /**< Gamma Set */
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#define LCD_CMD_DISPOFF 0x28 /**< Display OFF */
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#define LCD_CMD_DISPON 0x29 /**< Display ON */
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#define LCD_CMD_CASET 0x2A /**< Column Address Set */
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#define LCD_CMD_PASET 0x2b /**< Page Address Set */
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#define LCD_CMD_RAMWR 0x2c /**< Memory Write */
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#define LCD_CMD_RAMRD 0x2e /**< Memory Read */
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#define LCD_CMD_MADCTL 0x36 /**< Memory data access control */
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#define LCD_CMD_IDMOFF 0x38 /**< Idle Mode OFF */
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#define LCD_CMD_IDMON 0x39 /**< Idle Mode ON */
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#define LCD_CMD_TEOFF 0x34 /**< Tearing Effect Line Off */
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#define LCD_CMD_TEON 0x35 /**< Tearing Effect Line On */
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#define LCD_CMD_COLMOD 0x3A /**< Interface Pixel Format Set */
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#define LCD_CMD_PIXSET 0x3A /**< COLMOD: Pixel Format Set */
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#define LCD_CMD_RAMWRC 0x3c /**< Memory Write Continue */
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#define LCD_CMD_RAMRDC 0x3e /**< Memory Read Continue */
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#define LCD_CMD_WRDISBV 0x51 /**< Write Display Brightness */
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#define LCD_CMD_WRCTRLD 0x53 /**< Write Control Display */
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#define LCD_CMD_RDCTRLD 0x54 /**< Read Control Display */
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#define LCD_CMD_FRAMECTL1 0xb1 /**< Frame control normal*/
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#define LCD_CMD_FRAMECTL2 0xb2 /**< Frame control idle */
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#define LCD_CMD_FRAMECTL3 0xb3 /**< Frame control partial */
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#define LCD_CMD_DFUNC 0xb6 /**< Display function control */
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#define LCD_CMD_PWCTRL1 0xc0 /**< Power control 1 */
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#define LCD_CMD_PWCTRL2 0xc1 /**< Power control 2 */
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#define LCD_CMD_VMCTRL1 0xc5 /**< VCOM control 1 */
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#define LCD_CMD_VMCTRL2 0xc7 /**< VCOM control 2 */
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#define LCD_CMD_PGAMCTRL 0xe0 /**< Positive gamma correction */
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#define LCD_CMD_NGAMCTRL 0xe1 /**< Negative gamma correction */
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#define LCD_CMD_IFCTL 0xf6 /**< Interface control */
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/** @} */
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#define LCD_PIXSET_16BIT 0x55 /**< MCU and RGB 16 bit interface */
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#define LCD_PIXSET_18BIT 0x66 /**< MCU and RGB 18 bit interface (not implemented) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* LCD_INTERNAL_H */
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