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https://github.com/RIOT-OS/RIOT.git
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351 lines
13 KiB
C
351 lines
13 KiB
C
/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration for STM32 F0/F1/F3
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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#include "periph/gpio.h"
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/* PLL configuration */
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#if defined(CPU_FAM_STM32F1)
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define PLL_SRC (RCC_CFGR_PLLSRC) /* HSE */
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#else
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#define PLL_SRC (0) /* HSI / 2 */
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#endif
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/* RCC_CR_HSITRIM_4 is not defined on stm32f1 and corresponds to a value of 16.
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Use the same definition used for stm32f0/stm32f3 */
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#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
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#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMULL
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#define PLL_MUL ((CONFIG_CLOCK_PLL_MUL - 2) << RCC_CFGR_PLLMULL_Pos)
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#else /* CPU_FAM_STM32F0 && CPU_FAM_STM32F3 */
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#if CONFIG_BOARD_HAS_HSE
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#define PLL_SRC (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1)
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#else
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#define PLL_SRC (RCC_CFGR_PLLSRC_HSI_DIV2)
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#endif
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#define PLL_MUL ((CONFIG_CLOCK_PLL_MUL - 2) << RCC_CFGR_PLLMUL_Pos)
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#endif /* CPU_FAM_STM32F1 */
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#define PLL_PREDIV (CONFIG_CLOCK_PLL_PREDIV - 1)
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#define CLOCK_AHB_DIV (RCC_CFGR_HPRE_DIV1)
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#if defined(CPU_FAM_STM32F0)
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_DIV1)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_DIV2)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_DIV4)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_DIV8)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_DIV16)
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#else
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#error "Invalid APB prescaler value (only 1, 2, 4, 8 and 16 allowed)"
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#endif
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#else
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV2)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV4)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV8)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV16)
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#else
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#error "Invalid APB1 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
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#endif
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#if CONFIG_CLOCK_APB2_DIV == 1
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1)
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#elif CONFIG_CLOCK_APB2_DIV == 2
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV2)
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#elif CONFIG_CLOCK_APB2_DIV == 4
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV4)
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#elif CONFIG_CLOCK_APB2_DIV == 8
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV8)
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#elif CONFIG_CLOCK_APB2_DIV == 16
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV16)
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#else
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#error "Invalid APB2 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
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#endif
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#endif
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/* Configure MCO */
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#ifndef CONFIG_CLOCK_ENABLE_MCO
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#define CONFIG_CLOCK_ENABLE_MCO 0 /* Don't enable MCO by default */
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#endif
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/* Configure the MCO clock source: options are PLLCLK / 2 (default), HSE, HSI or SYSCLK*/
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#ifndef CONFIG_CLOCK_MCO_USE_PLLCLK
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
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IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK)
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#define CONFIG_CLOCK_MCO_USE_PLLCLK 0
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#else
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#define CONFIG_CLOCK_MCO_USE_PLLCLK 1 /* Use PLLCLK / 2 by default */
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#endif
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#endif /* CONFIG_CLOCK_MCO_USE_PLLCLK */
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#ifndef CONFIG_CLOCK_MCO_USE_HSE
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#define CONFIG_CLOCK_MCO_USE_HSE 0
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#endif /* CONFIG_CLOCK_MCO_USE_HSE */
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#ifndef CONFIG_CLOCK_MCO_USE_HSI
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#define CONFIG_CLOCK_MCO_USE_HSI 0
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#endif /* CONFIG_CLOCK_MCO_USE_HSI */
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#ifndef CONFIG_CLOCK_MCO_USE_SYSCLK
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#define CONFIG_CLOCK_MCO_USE_SYSCLK 0
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#endif /* CONFIG_CLOCK_MCO_USE_SYSCLK */
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
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IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
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#error "Cannot use PLLCLK as MCO clock source with other clocks"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) || \
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IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
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#error "Cannot use HSE as MCO clock source with other clocks"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) || \
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IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
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#error "Cannot use HSI as MCO clock source with other clocks"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
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IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK))
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#error "Cannot use SYSCLK as MCO clock source with other clocks"
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#endif
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/* Define MCO selection bitfields for F3, for compatibility reasons */
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#if defined(CPU_FAM_STM32F3)
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#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
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#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
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#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
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#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK)
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#define CLOCK_MCO_SRC (RCC_CFGR_MCOSEL_SYSCLK)
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#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI)
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#define CLOCK_MCO_SRC (RCC_CFGR_MCOSEL_HSI)
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#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE)
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#define CLOCK_MCO_SRC (RCC_CFGR_MCOSEL_HSE)
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#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK)
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#define CLOCK_MCO_SRC (RCC_CFGR_MCOSEL_PLL_DIV2)
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#else
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#error "Invalid MCO clock source selection"
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#endif
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/* Configure the MCO prescaler: valid values are 1, 2, 4, 8, 16, 32, 64, 128 */
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#ifndef CONFIG_CLOCK_MCO_PRE
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#define CONFIG_CLOCK_MCO_PRE (1)
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#endif
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/* MCO prescaler is only available on some STM32F0 and some STM32F3 lines */
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#if defined(CPU_LINE_STM32F030x6) || defined(CPU_LINE_STM32F030xC) || \
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defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F038xx) || \
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defined(CPU_LINE_STM32F042x6) || defined(CPU_LINE_STM32F048xx) || \
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defined(CPU_LINE_STM32F070x6) || defined(CPU_LINE_STM32F070xB) || \
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defined(CPU_LINE_STM32F071xB) || defined(CPU_LINE_STM32F072xB) || \
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defined(CPU_LINE_STM32F078xx) || defined(CPU_LINE_STM32F091xC) || \
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defined(CPU_LINE_STM32F098xx) || \
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defined(CPU_LINE_STM32F301x8) || defined(CPU_LINE_STM32F302x8) || \
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defined(CPU_LINE_STM32F302xE) || defined(CPU_LINE_STM32F303x8) || \
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defined(CPU_LINE_STM32F303xE) || defined(CPU_LINE_STM32F318xx) || \
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defined(CPU_LINE_STM32F328xx) || defined(CPU_LINE_STM32F334x8) || \
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defined(CPU_LINE_STM32F398xx)
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#if CONFIG_CLOCK_MCO_PRE == 1
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_DIV1)
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#elif CONFIG_CLOCK_MCO_PRE == 2
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_DIV2)
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#elif CONFIG_CLOCK_MCO_PRE == 4
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_DIV4)
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#elif CONFIG_CLOCK_MCO_PRE == 8
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_DIV8)
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#elif CONFIG_CLOCK_MCO_PRE == 16
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_DIV16)
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#elif CONFIG_CLOCK_MCO_PRE == 32
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_DIV32)
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#elif CONFIG_CLOCK_MCO_PRE == 64
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_DIV64)
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#elif CONFIG_CLOCK_MCO_PRE == 128
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_DIV128)
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#else
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#error "Invalid MCO prescaler"
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#endif
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#else /* CPU_FAM_STM32F1 and other F0/F3 lines */
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#if CONFIG_CLOCK_MCO_PRE != 1
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#error "MCO prescaler is not configurable on this CPU"
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#endif
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#define CLOCK_MCO_PRE (0)
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#endif
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/* MCO prescaler is only available on STM32F0 and STM32F3 */
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#if defined(CPU_FAM_STM32F1) && (CONFIG_CLOCK_MCO_PRE != 1)
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#error "MCO prescaler is not available on STM32F1 (only value 1 is allowed)."
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#endif
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/* Make sure MCO output clock is less than 50MHz, can only be possible when
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using SYSCLK driven by PLL */
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
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((CLOCK_CORECLOCK / CONFIG_CLOCK_MCO_PRE) > MHZ(50))
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#error "Cannot use a SYSCLK > 50MHz to output to MCO"
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#endif
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/* Check whether PLL is required */
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/* Check whether PLL must be enabled:
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- When PLLCLK is used as SYSCLK
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- When MCO is enabled with PLLCLK as input clock
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || \
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(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK))
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#define CLOCK_ENABLE_PLL 1
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#else
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#define CLOCK_ENABLE_PLL 0
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#endif
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/* Check whether HSE is required:
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- When HSE is used as SYSCLK
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- When PLL is used as SYSCLK and the board provides HSE (since HSE will be
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used as PLL input clock)
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- When MCO is enabled with HSE as input clock
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
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(IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) || \
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(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE))
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#define CLOCK_ENABLE_HSE 1
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#else
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#define CLOCK_ENABLE_HSE 0
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#endif
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/* Check whether HSI is required:
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- When HSI is used as SYSCLK
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- When PLL is used as SYSCLK and the board doesn't provide HSE (since HSI will be
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used as PLL input clock)
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- When MCO is enabled with HSI as input clock
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
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(!IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) || \
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(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI))
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#define CLOCK_ENABLE_HSI 1
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#else
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#define CLOCK_ENABLE_HSI 0
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#endif
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/* Deduct the needed flash wait states from the core clock frequency */
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#define FLASH_WAITSTATES ((CLOCK_CORECLOCK - 1) / MHZ(24))
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/* we enable I+D cashes, pre-fetch, and we set the actual number of
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* needed flash wait states */
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#define FLASH_ACR_CONFIG (FLASH_ACR_PRFTBE | FLASH_WAITSTATES)
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/** @} */
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void stmclk_init_sysclk(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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RCC->CIR = 0;
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/* enable HSI clock for the duration of initialization */
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stmclk_enable_hsi();
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/* use HSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configure by the board */
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#if defined(CPU_FAM_STM32F0)
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RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV);
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#else /* CPU_FAM_STM32F1 && CPU_FAM_STM32F3 */
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RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
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#endif /* CPU_FAM_STM32F0*/
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
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/* Flash config */
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FLASH->ACR = FLASH_ACR_CONFIG;
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/* disable all active clocks except HSI -> resets the clk configuration */
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RCC->CR = (RCC_CR_HSION | RCC_CR_HSITRIM_4);
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/* Enable and configure MCO if required */
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if (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO)) {
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RCC->CFGR |= (CLOCK_MCO_SRC | CLOCK_MCO_PRE);
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/* Configure MCO pin (PA8/AF0) */
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gpio_init(GPIO_PIN(PORT_A, 8), GPIO_OUT);
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#if defined(CPU_FAM_STM32F1)
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gpio_init_af(GPIO_PIN(PORT_A, 8), GPIO_AF_OUT_PP);
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#else
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gpio_init_af(GPIO_PIN(PORT_A, 8), GPIO_AF0);
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#endif
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}
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/* Enable HSE if it's used */
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if (IS_ACTIVE(CLOCK_ENABLE_HSE)) {
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RCC->CR |= (RCC_CR_HSEON);
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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}
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/* Enable PLL if it's used */
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if (IS_ACTIVE(CLOCK_ENABLE_PLL)) {
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RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL);
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/* set PLL configuration */
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RCC->CFGR |= (PLL_SRC | PLL_MUL);
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if (CONFIG_CLOCK_PLL_PREDIV == 2) {
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RCC->CFGR |= RCC_CFGR_PLLXTPRE; /* PREDIV == 2 */
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}
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#if !defined(CPU_FAM_STM32F1)
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else if (CONFIG_CLOCK_PLL_PREDIV > 2) {
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RCC->CFGR2 = PLL_PREDIV; /* PREDIV > 2 */
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}
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#endif
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RCC->CR |= (RCC_CR_PLLON);
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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}
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/* Configure SYSCLK */
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if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
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RCC->CFGR |= RCC_CFGR_SW_HSE;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
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}
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else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
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}
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if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
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/* Disable HSI only if not used */
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stmclk_disable_hsi();
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}
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irq_restore(is);
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}
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