mirror of
https://github.com/RIOT-OS/RIOT.git
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293 lines
10 KiB
C
293 lines
10 KiB
C
/*
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* Copyright (C) 2024 BISSELL Homecare, Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration for the C0 family
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*
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* @author Jason Parker <Jason.Parker@bissell.com>
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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#include "periph/gpio.h"
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#if defined(CPU_FAM_STM32C0)
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#define RCC_CFGR_SW_HSI (0)
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#define RCC_CFGR_SW_HSE (RCC_CFGR_SW_0)
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#if CONFIG_CLOCK_HSISYS_DIV == 1
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#define CLOCK_HSI_DIV (0)
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#elif CONFIG_CLOCK_HSISYS_DIV == 2
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_0)
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#elif CONFIG_CLOCK_HSISYS_DIV == 4
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_1)
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#elif CONFIG_CLOCK_HSISYS_DIV == 8
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)
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#elif CONFIG_CLOCK_HSISYS_DIV == 16
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2)
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#elif CONFIG_CLOCK_HSISYS_DIV == 32
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0)
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#elif CONFIG_CLOCK_HSISYS_DIV == 64
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1)
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#elif CONFIG_CLOCK_HSISYS_DIV == 128
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#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)
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#endif
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#define CLOCK_AHB_DIV (0)
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (0)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_2)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0)
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#endif
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#endif /* CPU_FAM_STM32C0 */
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/* Configure MCO */
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#ifndef CONFIG_CLOCK_ENABLE_MCO
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#define CONFIG_CLOCK_ENABLE_MCO 0 /* Don't enable MCO by default */
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#endif
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/* Configure the MCO clock source: options are HSE, HSI (default), LSE, LSI or SYSCLK*/
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#define CONFIG_CLOCK_MCO_USE_PLLCLK 0 // PLL not supported in STM32C0
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#ifndef CONFIG_CLOCK_MCO_USE_HSE
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#define CONFIG_CLOCK_MCO_USE_HSE 0
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#endif /* CONFIG_CLOCK_MCO_USE_HSE */
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#ifndef CONFIG_CLOCK_MCO_USE_HSI
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#define CONFIG_CLOCK_MCO_USE_HSI 1
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#endif /* CONFIG_CLOCK_MCO_USE_HSI */
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#ifndef CONFIG_CLOCK_MCO_USE_LSE
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#define CONFIG_CLOCK_MCO_USE_LSE 0
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#endif /* CONFIG_CLOCK_MCO_USE_LSE */
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#ifndef CONFIG_CLOCK_MCO_USE_LSI
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#define CONFIG_CLOCK_MCO_USE_LSI 0
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#endif /* CONFIG_CLOCK_MCO_USE_LSI */
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#ifndef CONFIG_CLOCK_MCO_USE_SYSCLK
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#define CONFIG_CLOCK_MCO_USE_SYSCLK 0
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#endif /* CONFIG_CLOCK_MCO_USE_SYSCLK */
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || \
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IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
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#error "Cannot use HSE as MCO clock source with other clocks"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || \
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IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
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#error "Cannot use HSI as MCO clock source with other clocks"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
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IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
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#error "Cannot use LSE as MCO clock source with other clocks"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
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IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
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#error "Cannot use LSI as MCO clock source with other clocks"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
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IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI))
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#error "Cannot use SYSCLK as MCO clock source with other clocks"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK)
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#define CLOCK_MCO_SRC (RCC_CFGR_MCOSEL_0)
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#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI)
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#define CLOCK_MCO_SRC (RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_0)
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#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE)
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#define CLOCK_MCO_SRC (RCC_CFGR_MCOSEL_2)
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#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI)
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#define CLOCK_MCO_SRC (RCC_CFGR_MCOSEL_2 | RCC_CFGR_MCOSEL_1)
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#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE)
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#define CLOCK_MCO_SRC (RCC_CFGR_MCOSEL_2 | RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_0)
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#else
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#error "Invalid MCO clock source selection"
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#endif
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/* Configure the MCO prescaler */
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#ifndef CONFIG_CLOCK_MCO_PRE
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#define CONFIG_CLOCK_MCO_PRE (1)
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#endif
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/* Define MCO prescalers */
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#if CONFIG_CLOCK_MCO_PRE == 1
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#define CLOCK_MCO_PRE (0)
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#elif CONFIG_CLOCK_MCO_PRE == 2
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_0)
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#elif CONFIG_CLOCK_MCO_PRE == 4
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_1)
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#elif CONFIG_CLOCK_MCO_PRE == 8
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
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#elif CONFIG_CLOCK_MCO_PRE == 16
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_2)
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#elif CONFIG_CLOCK_MCO_PRE == 32
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)
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#elif CONFIG_CLOCK_MCO_PRE == 64
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)
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#elif CONFIG_CLOCK_MCO_PRE == 128
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#define CLOCK_MCO_PRE (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
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#else
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#error "Invalid MCO prescaler"
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#endif
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/* PLL not supported in STM32C0 */
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#define CLOCK_ENABLE_PLL 0
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/* Check whether HSE is required:
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- When HSE is used as SYSCLK
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- When HSE is used as MCO clock source
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
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(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE))
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#define CLOCK_ENABLE_HSE 1
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#else
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#define CLOCK_ENABLE_HSE 0
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#endif
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/* Check whether HSI is required:
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- When HSI is used as SYSCLK
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- When HSI is used as MCO clock source
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
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(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI))
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#define CLOCK_ENABLE_HSI 1
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#else
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#define CLOCK_ENABLE_HSI 0
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#endif
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/* Check whether LSE must be enabled */
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#if IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE)
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#define CLOCK_ENABLE_LSE 1
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#else
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#define CLOCK_ENABLE_LSE 0
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#endif
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/* Check whether LSI must be enabled */
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#if IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI)
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#define CLOCK_ENABLE_LSI 1
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#else
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#define CLOCK_ENABLE_LSI 0
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#endif
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/** Determine the required flash wait states from the core clock frequency */
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#if CLOCK_CORECLOCK >= 24000000
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#define FLASH_WAITSTATES (FLASH_ACR_LATENCY_0) /* 1 wait states */
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#else
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#define FLASH_WAITSTATES (0) /* 0 wait states */
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#endif
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void stmclk_init_sysclk(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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/* enable HSI clock for the duration of initialization */
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stmclk_enable_hsi();
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RCC->CIER = 0;
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/* use HSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configured by the board */
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RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
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/* we enable instruction cache, pre-fetch, and we set the required flash wait states */
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FLASH->ACR |= (FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES);
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/* disable all active clocks except HSI -> resets the clk configuration */
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RCC->CR = RCC_CR_HSION;
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if (IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && CONFIG_CLOCK_HSISYS_DIV != 1) {
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/* configure HSISYS divider */
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RCC->CR |= CLOCK_HSI_DIV;
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while (!(RCC->CR & RCC_CR_HSIRDY)) {}
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}
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/* Enable HSE if required */
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if (IS_ACTIVE(CLOCK_ENABLE_HSE)) {
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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}
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/* Configure SYSCLK */
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if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
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RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV);
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RCC->CFGR |= RCC_CFGR_SW_HSE;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
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}
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if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
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/* Disable HSI only if not used */
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stmclk_disable_hsi();
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}
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/* Enable the LSE if required for MCO
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* If available on the board, LSE might also be initialized for RTT/RTC
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* peripherals. For the monent, this initialization is done in the
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* corresponding peripheral drivers. */
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if (IS_ACTIVE(CLOCK_ENABLE_LSE)) {
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stmclk_dbp_unlock();
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RCC->CSR1 |= RCC_CSR1_LSEON;
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while (!(RCC->CSR1 & RCC_CSR1_LSERDY)) {}
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stmclk_dbp_lock();
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}
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/* Enable the LSI if required for MCO
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* If no LSE is available on the board, LSI might also be initialized for
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* RTT/RTC peripherals. For the monent, this initialization is done in the
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* corresponding peripheral drivers. */
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if (IS_ACTIVE(CLOCK_ENABLE_LSI)) {
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RCC->CSR2 |= RCC_CSR2_LSION;
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while (!(RCC->CSR2 & RCC_CSR2_LSIRDY)) {}
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}
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/* Configure MCO */
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if (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO)) {
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/* As stated in the manual, it is highly recommended to change the MCO
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prescaler before enabling the MCO */
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RCC->CFGR |= CLOCK_MCO_PRE;
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RCC->CFGR |= CLOCK_MCO_SRC;
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/* Configure MCO pin (PA8 with AF0) */
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gpio_init(GPIO_PIN(PORT_A, 8), GPIO_OUT);
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gpio_init_af(GPIO_PIN(PORT_A, 8), GPIO_AF0);
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}
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#if IS_USED(MODULE_PERIPH_HWRNG)
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/* HWRNG is clocked by HSI48 so enable this clock when the peripheral is used */
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RCC->CRRCR |= RCC_CRRCR_HSI48ON;
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while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) {}
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#endif
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irq_restore(is);
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}
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