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49 lines
1.3 KiB
Plaintext
49 lines
1.3 KiB
Plaintext
# Copyright (c) 2022 HAW Hamburg
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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#
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if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1
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choice
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bool "Main PLL division factor (PLLP) for main system clock" if CUSTOM_PLL_PARAMS
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default PLL_P_DIV_4 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
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default PLL_P_DIV_2
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config PLL_P_DIV_2
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bool "Divide by 2"
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config PLL_P_DIV_4
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bool "Divide by 4"
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config PLL_P_DIV_6
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bool "Divide by 6"
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config PLL_P_DIV_8
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bool "Divide by 8"
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endchoice
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config CLOCK_PLL_P
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int
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default 3 if CPU_FAM_MP1
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default 2 if PLL_P_DIV_2
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default 4 if PLL_P_DIV_4
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default 6 if PLL_P_DIV_6
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default 8 if PLL_P_DIV_8
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config CLOCK_PLL_Q
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int "Main PLL division factor (PLLQ) for USB OTG FS, and SDIO clocks" if CUSTOM_PLL_PARAMS
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default 5 if CPU_FAM_F2
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default 7 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
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default 4 if CPU_FAM_F4 && CLOCK_MAX_100MHZ
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default 7 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
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default 9 if CPU_FAM_F7
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default 13 if CPU_FAM_MP1
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default 8
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range 2 15
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endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1
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