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113 lines
3.1 KiB
C
113 lines
3.1 KiB
C
/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam3
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @}
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*/
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#include "cpu.h"
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#include "kernel_init.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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#include "stdio_base.h"
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/**
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* @brief Keys needed for editing certain PMC registers
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* @{
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*/
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#define WPKEY (0x504D43)
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#define MORKEY (0x37)
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/** @} */
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/**
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* @brief Key for writing the SUPC control register
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*/
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#define SUPCKEY (0xa5)
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/**
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* @brief Start-up time for external crystal (will be multiplied by 8)
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*/
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#define XTAL_STARTUP (8U)
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/**
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* @brief PLL is incremented to this value until considered stable
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*/
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#define PLL_CNT (64U)
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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/* disable the watchdog timer */
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WDT->WDT_MR |= WDT_MR_WDDIS;
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/* initialize the Cortex-M core */
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cortexm_init();
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/* setup the flash wait states */
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EFC0->EEFC_FMR = EEFC_FMR_FWS(CLOCK_FWS);
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EFC1->EEFC_FMR = EEFC_FMR_FWS(CLOCK_FWS);
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/* unlock write protect register for PMC module */
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PMC->PMC_WPMR = PMC_WPMR_WPKEY(WPKEY);
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/* activate the external crystal */
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PMC->CKGR_MOR = (CKGR_MOR_KEY(MORKEY) |
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CKGR_MOR_MOSCXTST(XTAL_STARTUP) |
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CKGR_MOR_MOSCXTEN |
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CKGR_MOR_MOSCRCEN);
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/* wait for crystal to be stable */
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while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
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/* select crystal to clock the main clock */
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PMC->CKGR_MOR = (CKGR_MOR_KEY(MORKEY) |
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CKGR_MOR_MOSCXTST(XTAL_STARTUP) |
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CKGR_MOR_MOSCXTEN |
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CKGR_MOR_MOSCRCEN |
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CKGR_MOR_MOSCSEL);
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/* wait for main oscillator selection to be complete */
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while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
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/* setup PLLA */
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PMC->CKGR_PLLAR = (CKGR_PLLAR_ONE |
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CKGR_PLLAR_PLLACOUNT(PLL_CNT) |
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CKGR_PLLAR_MULA(CLOCK_PLL_MUL) |
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CKGR_PLLAR_DIVA(CLOCK_PLL_DIV));
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/* wait for PLL to lock */
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while (!(PMC->PMC_SR & PMC_SR_LOCKA));
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/* before switching to PLLA, we need to switch to main clock */
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PMC->PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
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/* use PLLA as main clock source */
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PMC->PMC_MCKR = PMC_MCKR_CSS_PLLA_CLK;
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/* wait for master clock to be ready */
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
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/* setup the SCLK: switch to external oscillator if applicable */
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#if CLOCK_SCLK_XTAL
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/* enable external oscillator */
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SUPC->SUPC_CR = (SUPC_CR_KEY(SUPCKEY) | SUPC_CR_XTALSEL);
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while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST)) {}
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#endif
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/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
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early_init();
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/* trigger static peripheral initialization */
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periph_init();
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}
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