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62 lines
1.4 KiB
C
62 lines
1.4 KiB
C
/*
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* Copyright (C) 2020, Koen Zandberg <koen@bergzand.net>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_riscv_common
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* @{
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*
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* @file cpu.c
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* @brief Common CPU initialization for RISC-V rv32i architecture
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*
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* @author Koen Zandberg <koen@bergzand.net>
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* @}
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*/
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#include "cpu.h"
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#include "cpu_conf_common.h"
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#include "periph_cpu_common.h"
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#ifdef MODULE_PMP_NOEXEC_RAM
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#include "pmp.h"
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#endif
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#ifdef MODULE_PUF_SRAM
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#include "puf_sram.h"
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extern unsigned _sheap;
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void riscv_puf_sram_init(void)
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{
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puf_sram_init((uint8_t *)&_sheap, SEED_RAM_LEN);
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}
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#endif /* MODULE_PUF_SRAM */
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void riscv_fpu_init(void)
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{
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/* Enable FPU if present */
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if (read_csr(misa) & (1 << ('F' - 'A'))) {
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write_csr(mstatus, MSTATUS_FS); /* allow FPU instructions without trapping */
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write_csr(fcsr, 0); /* initialize rounding mode, undefined at reset */
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}
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}
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void riscv_init(void)
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{
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riscv_fpu_init();
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riscv_irq_init();
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#ifdef MODULE_PMP_NOEXEC_RAM
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/* This marks the (main) RAM region as non
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* executable. Using PMP entry 0.
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*/
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write_pmpaddr(0, make_napot(CPU_RAM_BASE, CPU_RAM_SIZE));
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/* Lock & select NAPOT, only allow write and read */
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set_pmpcfg(0, PMP_L | PMP_NAPOT | PMP_W | PMP_R);
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#endif
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}
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