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138 lines
3.3 KiB
C
138 lines
3.3 KiB
C
/*
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* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_riscv_common
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* @{
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*
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* @file
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* @brief Platform-Level interrupt controller driver
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*
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* RISCV implementations using this peripheral must define the `PLIC_BASE_ADDR`,
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* in order to use the PLIC as interrupt controller. Also required are:
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* PLIC_NUM_INTERRUPTS and PLIC_NUM_PRIORITIES (future compatibility).
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*
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* @author Koen Zandberg <koen@bergzand.net>
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* @}
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*/
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#include <assert.h>
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#include "vendor/riscv_csr.h"
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#include "assert.h"
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#include "cpu.h"
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#include "plic.h"
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#include "architecture.h"
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/* Local macros to calculate register offsets */
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#ifndef _REG32
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#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
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#endif
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#ifndef PLIC_REG
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#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
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#endif
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/* PLIC external ISR function list */
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static plic_isr_cb_t _ext_isrs[PLIC_NUM_INTERRUPTS];
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static inline volatile uint32_t *_get_claim_complete_addr(void)
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{
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uword_t hart_id = read_csr(mhartid);
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/* Construct the claim address */
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return &PLIC_REG(PLIC_CLAIM_OFFSET +
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(hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));
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}
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static inline volatile uint32_t *_get_threshold_addr(void)
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{
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uword_t hart_id = read_csr(mhartid);
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/* Construct the claim address */
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return &PLIC_REG(PLIC_THRESHOLD_OFFSET +
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(hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET));
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}
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static inline volatile uint32_t *_get_irq_reg(unsigned irq)
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{
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uword_t hart_id = read_csr(mhartid);
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return &PLIC_REG(PLIC_ENABLE_OFFSET +
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(hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)) +
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(irq >> 5); /* Intentionally outside the PLIC_REG macro */
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}
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void plic_enable_interrupt(unsigned irq)
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{
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volatile uint32_t *irq_reg = _get_irq_reg(irq);
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__atomic_fetch_or(irq_reg, 1 << (irq & 0x1f), __ATOMIC_RELAXED);
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}
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void plic_disable_interrupt(unsigned irq)
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{
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volatile uint32_t *irq_reg = _get_irq_reg(irq);
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__atomic_fetch_and(irq_reg, ~(1 << (irq & 0x1f)), __ATOMIC_RELAXED);
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}
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void plic_set_threshold(unsigned threshold)
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{
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volatile uint32_t *plic_threshold = _get_threshold_addr();
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*plic_threshold = threshold;
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}
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void plic_set_priority(unsigned irq, unsigned priority)
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{
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assert(irq <= PLIC_NUM_INTERRUPTS);
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assert(irq != 0);
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*(&PLIC_REG(PLIC_PRIORITY_OFFSET) + irq) = priority;
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}
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static void plic_complete_interrupt(unsigned irq)
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{
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volatile uint32_t *complete_addr = _get_claim_complete_addr();
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*complete_addr = irq;
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}
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static unsigned plic_claim_interrupt(void)
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{
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return *_get_claim_complete_addr();
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}
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void plic_set_isr_cb(unsigned irq, plic_isr_cb_t cb)
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{
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assert(irq <= PLIC_NUM_INTERRUPTS);
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assert(irq != 0);
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_ext_isrs[irq] = cb;
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}
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void plic_init(void)
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{
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for (unsigned i = 1; i <= PLIC_NUM_INTERRUPTS; i++) {
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plic_disable_interrupt(i);
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plic_set_priority(i, 0);
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}
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plic_set_threshold(0);
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}
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void plic_isr_handler(void)
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{
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unsigned irq = plic_claim_interrupt();
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/* Don't check here, just crash hard if no handler is available */
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_ext_isrs[irq](irq);
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plic_complete_interrupt(irq);
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}
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