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https://github.com/RIOT-OS/RIOT.git
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Koen Zandberg
48aa533639
The CLIC is a next generation interrupt controller for the RISC-V architecture. Co-authored-by:
71 lines
1.6 KiB
C
71 lines
1.6 KiB
C
/*
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* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_riscv_common
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* @{
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*
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* @file
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* @brief RISCV CLIC interrupt controller implementation
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*
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* @author Koen Zandberg <koen@bergzand.net>
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*/
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#include <stdint.h>
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#include <assert.h>
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#include "clic.h"
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/**
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* @brief CLIC registry offset helper
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*/
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#define CLIC_REGP(offset) ((volatile uint32_t *)((CLIC_BASE_ADDR) + (offset)))
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/**
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* @name CLIC configuration registers
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* @{
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*/
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#define CLIC_CFG *((volatile uint8_t *)CLIC_REGP(0x0))
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#define CLIC_INFO *((volatile uint32_t *)CLIC_REGP(0x4)
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#define CLIC_MTH *((volatile uint8_t *)CLIC_REGP(0xb)
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#define CLIC_INT_ADDR CLIC_REGP(0x1000)
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#define CLIC_INT ((volatile clic_clicint_t *)CLIC_INT_ADDR)
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/** @} */
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/* PLIC external ISR function list */
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static clic_isr_cb_t _ext_isrs[CLIC_NUM_INTERRUPTS];
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void clic_init(void)
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{}
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void clic_enable_interrupt(unsigned irq, unsigned priority)
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{
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CLIC_INT[irq].ie = 1;
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CLIC_INT[irq].attr = 0;
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clic_set_priority(irq, priority);
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}
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void clic_disable_interrupt(unsigned irq)
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{
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CLIC_INT[irq].ie = 0;
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}
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void clic_set_priority(unsigned irq, unsigned priority)
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{
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CLIC_INT[irq].ctl = priority;
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}
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void clic_set_handler(unsigned irq, clic_isr_cb_t cb)
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{
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assert(irq < CLIC_NUM_INTERRUPTS);
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_ext_isrs[irq] = cb;
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}
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void clic_isr_handler(uint32_t irq)
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{
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_ext_isrs[irq](irq);
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}
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