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32 lines
805 B
Plaintext
32 lines
805 B
Plaintext
/*
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* Copyright (C) 2017, 2019 Ken Rabold
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_riscv_common
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* @{
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*
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* @file
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* @brief Memory definitions for the RISC-V CPU
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*
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* @author Ken Rabold
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* @author Koen Zandberg <koen@bergzand.net>
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*
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* @}
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*/
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INCLUDE riscv_vars.ld
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MEMORY
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{
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flash (rxai!w) : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _fw_rom_length
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ram (wxa!ri) : ORIGIN = _ram_start_addr, LENGTH = _ram_length
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itim (wxa!ri) : ORIGIN = _itim_start_addr, LENGTH = _itim_length
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rom_aux (rx) : ORIGIN = _rom_start_addr + _slot_aux_offset, LENGTH = _slot_aux_len
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}
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INCLUDE riscv_base.ld
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