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65 lines
1.2 KiB
C
65 lines
1.2 KiB
C
/*
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* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_riscv_common
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* @{
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*
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* @file
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* @brief RISC-V CPU configuration options
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*
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* @author Koen Zandberg
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*/
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#ifndef CPU_CONF_COMMON_H
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#define CPU_CONF_COMMON_H
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#include "vendor/riscv_csr.h"
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#include "cpu_conf_common.h"
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/**
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* @name Configuration of default stack sizes
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* @{
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*/
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#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
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#define THREAD_EXTRA_STACKSIZE_PRINTF (256)
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#endif
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#ifndef THREAD_STACKSIZE_DEFAULT
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#define THREAD_STACKSIZE_DEFAULT (1024)
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#endif
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#ifndef THREAD_STACKSIZE_IDLE
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#define THREAD_STACKSIZE_IDLE (256)
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#endif
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/** @} */
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/**
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* @brief Attribute for memory sections required by SRAM PUF
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*/
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#define PUF_SRAM_ATTRIBUTES __attribute__((used, section(".noinit")))
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/**
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* @brief Declare the heap_stats function as available
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*/
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#define HAVE_HEAP_STATS
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/**
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* @brief This arch uses the inlined irq API.
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*/
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#define IRQ_API_INLINED (1)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_COMMON_H */
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/** @} */
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