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https://github.com/RIOT-OS/RIOT.git
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157 lines
4.4 KiB
C
157 lines
4.4 KiB
C
/*
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* Copyright (C) 2009 Kaspar Schleiser <kaspar@schleiser.de>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*
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* Parts taken from FeuerWhere-Project, lpc2387.h.
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*/
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#ifndef LPC23XX_H
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#define LPC23XX_H
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#include "vendor/lpc23xx.h"
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#include "arm7_common.h"
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#include "bitarithm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define F_CCO 288000000
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#define CL_CPU_DIV 4 ///< CPU clock divider
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#define F_RC_OSCILLATOR 4000000 ///< Frequency of internal RC oscillator
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#define F_RTC_OSCILLATOR 32767 ///< Frequency of RTC oscillator
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#define VIC_SIZE 32
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#define PLLCFG_N(n) ((n - 1) << 16)
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#define PLLCFG_M(m) (m - 1)
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#define GPIO_INT 17
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#define IRQP_GPIO 4
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#define _XTAL (72000)
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/**
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* @name RTC constants
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* @{
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*/
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#define IMSEC 0x00000001
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#define IMMIN 0x00000002
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#define IMHOUR 0x00000004
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#define IMDOM 0x00000008
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#define IMDOW 0x00000010
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#define IMDOY 0x00000020
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#define IMMON 0x00000040
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#define IMYEAR 0x00000080
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#define AMRSEC 0x00000001 /* Alarm mask for Seconds */
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#define AMRMIN 0x00000002 /* Alarm mask for Minutes */
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#define AMRHOUR 0x00000004 /* Alarm mask for Hours */
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#define AMRDOM 0x00000008 /* Alarm mask for Day of Month */
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#define AMRDOW 0x00000010 /* Alarm mask for Day of Week */
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#define AMRDOY 0x00000020 /* Alarm mask for Day of Year */
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#define AMRMON 0x00000040 /* Alarm mask for Month */
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#define AMRYEAR 0x00000080 /* Alarm mask for Year */
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#define ILR_RTCCIF BIT0
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#define ILR_RTCALF BIT1
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#define ILR_RTSSF BIT2
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#define CCR_CLKEN 0x01
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#define CCR_CTCRST 0x02
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#define CCR_CLKSRC 0x10
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/** @} */
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/**
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* @name WD constants
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* @{
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*/
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#define WDEN BIT0
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#define WDRESET BIT1
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#define WDTOF BIT2
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#define WDINT BIT3
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/** @} */
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/**
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* @name INTWAKE Constants
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* @{
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*/
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#define EXTWAKE0 BIT0
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#define EXTWAKE1 BIT1
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#define EXTWAKE2 BIT2
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#define EXTWAKE3 BIT3
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#define ETHWAKE BIT4
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#define USBWAKE BIT5
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#define CANWAKE BIT6
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#define GPIO0WAKE BIT7
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#define GPIO2WAKE BIT8
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#define BODWAKE BIT14
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#define RTCWAKE BIT15
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/** @} */
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/**
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* @name UART Constants
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* @{
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*/
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#define ULSR_RDR BIT0
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#define ULSR_OE BIT1
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#define ULSR_PE BIT2
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#define ULSR_FE BIT3
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#define ULSR_BI BIT4
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#define ULSR_THRE BIT5
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#define ULSR_TEMT BIT6
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#define ULSR_RXFE BIT7
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#define UIIR_INT_STATUS (BIT0) ///< Interrupt Status
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#define UIIR_THRE_INT (BIT1) ///< Transmit Holding Register Empty
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#define UIIR_RDA_INT (BIT2) ///< Receive Data Available
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#define UIIR_RLS_INT (BIT1 | BIT2) ///< Receive Line Status
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#define UIIR_CTI_INT (BIT2 | BIT3) ///< Character Timeout Indicator
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#define UIIR_ID_MASK (BIT1 | BIT2 | BIT3)
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#define UIIR_ABEO_INT BIT8
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#define UIIR_ABTO_INT BIT9
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/** @} */
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/**
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* @name SSP Status Register Constants
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* @{
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*/
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#define SSPSR_TFE BIT0 ///< Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
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#define SSPSR_TNF BIT1 ///< Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
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#define SSPSR_RNE BIT2 ///< Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
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#define SSPSR_RFF BIT3 ///< Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
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#define SSPSR_BSY BIT4 ///< Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
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/** @} */
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/**
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* @name Timer register offsets
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* @{
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*/
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#define TXIR 0x00
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#define TXTCR 0x04
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#define TXTC 0x08 ///< Timer counter
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#define TXPR 0x0C
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#define TXPC 0x10
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#define TXMCR 0x14
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#define TXMR0 0x18
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#define TXMR1 0x1C
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#define TXMR2 0x20
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#define TXMR3 0x24
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#define TXCCR 0x28
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#define TXCR0 0x2C
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#define TXCR1 0x30
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#define TXCR2 0x34
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#define TXCR3 0x38
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#define TXEMR 0x3C
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#define TXCTCR 0x70
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* LPC23XX_H */
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