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https://github.com/RIOT-OS/RIOT.git
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99 lines
3.3 KiB
C
99 lines
3.3 KiB
C
/**************************************************************************//**
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* @file
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
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* for the NXP LPC17xx Device Series
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* @version V1.09
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* @date 09. November 2013
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*
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* @note Integrated, adopted, and renamed for RIOT by Oliver Hahm.
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*
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include "vendor/LPC17xx.h"
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#include "vendor/conf.h"
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/**
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* Initialize the system
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*
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* @brief Setup the microcontroller system.
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* Initialize the System. */
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void SystemInit(void)
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{
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#if (CLOCK_SETUP) /* Clock Setup */
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LPC_SC->SCS = SCS_Val;
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if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
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while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
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}
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LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
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LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
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LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
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LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
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#if (PLL0_SETUP)
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LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
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LPC_SC->PLL0FEED = 0xAA;
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LPC_SC->PLL0FEED = 0x55;
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LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
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LPC_SC->PLL0FEED = 0xAA;
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LPC_SC->PLL0FEED = 0x55;
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while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
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LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
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LPC_SC->PLL0FEED = 0xAA;
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LPC_SC->PLL0FEED = 0x55;
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while (!(LPC_SC->PLL0STAT & ((1 << 25) | (1 << 24)))); /* Wait for PLLC0_STAT & PLLE0_STAT */
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#endif
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#if (PLL1_SETUP)
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LPC_SC->PLL1CFG = PLL1CFG_Val;
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LPC_SC->PLL1FEED = 0xAA;
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LPC_SC->PLL1FEED = 0x55;
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LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
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LPC_SC->PLL1FEED = 0xAA;
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LPC_SC->PLL1FEED = 0x55;
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while (!(LPC_SC->PLL1STAT & (1 << 10))); /* Wait for PLOCK1 */
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LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
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LPC_SC->PLL1FEED = 0xAA;
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LPC_SC->PLL1FEED = 0x55;
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while (!(LPC_SC->PLL1STAT & ((1 << 9) | (1 << 8)))); /* Wait for PLLC1_STAT & PLLE1_STAT */
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#else
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LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
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#endif
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LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
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LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
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#endif
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#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
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LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
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#endif
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}
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