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Many MCUs contain some Backup or Low Power SRAM that is retained'even
in the deepest sleep modes.
In such sleep modes the MCU is essentually turned off with only the RTC
still running.
It can be woken by a GPIO or a RTC alarm. When this happens, a reset is
triggered and the normal startup routine is invoked.
This adds bss & data section for this memory in the linker script.
This allows for structures to be placed in it e.g.:
e.g.:
static uint8_t persistent_buffer[64] __attribute__((section(".backup.bss")));
static uint32_t persistent_counter __attribute__((section(".backup.data"))) = 1234;
32 lines
760 B
Plaintext
32 lines
760 B
Plaintext
/*
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* Copyright (C) 2017 Inria
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* 2018 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_cortexm_common
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* @{
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*
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* @file
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* @brief Memory definitions for the Cortex-M family
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*
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* @author Francisco Acosta <francisco.acosta@inria.fr>
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* Gaëtan Harter <gaetan.harter@inria.fr>
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*
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* @}
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*/
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INCLUDE cortexm_rom_offset.ld
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MEMORY
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{
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rom (rx) : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _fw_rom_length
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ram (w!rx) : ORIGIN = _ram_start_addr, LENGTH = _ram_length
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}
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INCLUDE cortexm_base.ld
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