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729 lines
31 KiB
C
729 lines
31 KiB
C
/******************************************************************************
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* Filename: hw_i2c_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_I2C_H__
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#define __HW_I2C_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// I2C component
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//
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//*****************************************************************************
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// Slave Own Address
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#define I2C_O_SOAR 0x00000000
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// Slave Status
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#define I2C_O_SSTAT 0x00000004
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// Slave Control
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#define I2C_O_SCTL 0x00000004
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// Slave Data
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#define I2C_O_SDR 0x00000008
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// Slave Interrupt Mask
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#define I2C_O_SIMR 0x0000000C
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// Slave Raw Interrupt Status
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#define I2C_O_SRIS 0x00000010
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// Slave Masked Interrupt Status
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#define I2C_O_SMIS 0x00000014
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// Slave Interrupt Clear
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#define I2C_O_SICR 0x00000018
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// Master Salve Address
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#define I2C_O_MSA 0x00000800
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// Master Status
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#define I2C_O_MSTAT 0x00000804
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// Master Control
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#define I2C_O_MCTRL 0x00000804
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// Master Data
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#define I2C_O_MDR 0x00000808
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// I2C Master Timer Period
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#define I2C_O_MTPR 0x0000080C
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// Master Interrupt Mask
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#define I2C_O_MIMR 0x00000810
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// Master Raw Interrupt Status
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#define I2C_O_MRIS 0x00000814
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// Master Masked Interrupt Status
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#define I2C_O_MMIS 0x00000818
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// Master Interrupt Clear
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#define I2C_O_MICR 0x0000081C
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// Master Configuration
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#define I2C_O_MCR 0x00000820
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//*****************************************************************************
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//
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// Register: I2C_O_SOAR
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//
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//*****************************************************************************
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// Field: [6:0] OAR
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//
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// I2C slave own address
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// This field specifies bits a6 through a0 of the slave address.
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#define I2C_SOAR_OAR_W 7
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#define I2C_SOAR_OAR_M 0x0000007F
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#define I2C_SOAR_OAR_S 0
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//*****************************************************************************
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//
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// Register: I2C_O_SSTAT
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//
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//*****************************************************************************
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// Field: [2] FBR
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//
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// First byte received
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//
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// 0: The first byte has not been received.
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// 1: The first byte following the slave's own address has been received.
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//
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// This bit is only valid when the RREQ bit is set and is automatically cleared
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// when data has been read from the SDR register.
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// Note: This bit is not used for slave transmit operations.
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#define I2C_SSTAT_FBR 0x00000004
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#define I2C_SSTAT_FBR_BITN 2
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#define I2C_SSTAT_FBR_M 0x00000004
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#define I2C_SSTAT_FBR_S 2
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// Field: [1] TREQ
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//
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// Transmit request
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//
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// 0: No outstanding transmit request.
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// 1: The I2C controller has been addressed as a slave transmitter and is using
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// clock stretching to delay the master until data has been written to the SDR
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// register.
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#define I2C_SSTAT_TREQ 0x00000002
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#define I2C_SSTAT_TREQ_BITN 1
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#define I2C_SSTAT_TREQ_M 0x00000002
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#define I2C_SSTAT_TREQ_S 1
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// Field: [0] RREQ
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//
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// Receive request
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//
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// 0: No outstanding receive data
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// 1: The I2C controller has outstanding receive data from the I2C master and
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// is using clock stretching to delay the master until data has been read from
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// the SDR register.
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#define I2C_SSTAT_RREQ 0x00000001
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#define I2C_SSTAT_RREQ_BITN 0
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#define I2C_SSTAT_RREQ_M 0x00000001
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#define I2C_SSTAT_RREQ_S 0
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//*****************************************************************************
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//
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// Register: I2C_O_SCTL
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//
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//*****************************************************************************
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// Field: [0] DA
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//
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// Device active
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//
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// 0: Disables the I2C slave operation
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// 1: Enables the I2C slave operation
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#define I2C_SCTL_DA 0x00000001
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#define I2C_SCTL_DA_BITN 0
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#define I2C_SCTL_DA_M 0x00000001
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#define I2C_SCTL_DA_S 0
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//*****************************************************************************
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//
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// Register: I2C_O_SDR
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//
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//*****************************************************************************
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// Field: [7:0] DATA
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//
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// Data for transfer
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// This field contains the data for transfer during a slave receive or transmit
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// operation. When written the register data is used as transmit data. When
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// read, this register returns the last data received.
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// Data is stored until next update, either by a system write for transmit or
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// by an external master for receive.
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#define I2C_SDR_DATA_W 8
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#define I2C_SDR_DATA_M 0x000000FF
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#define I2C_SDR_DATA_S 0
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//*****************************************************************************
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//
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// Register: I2C_O_SIMR
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//
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//*****************************************************************************
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// Field: [2] STOPIM
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//
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// Stop condition interrupt mask
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//
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// 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt
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// controller.
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// 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt
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// controller.
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// ENUMs:
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// EN Enable Interrupt
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// DIS Disable Interrupt
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#define I2C_SIMR_STOPIM 0x00000004
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#define I2C_SIMR_STOPIM_BITN 2
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#define I2C_SIMR_STOPIM_M 0x00000004
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#define I2C_SIMR_STOPIM_S 2
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#define I2C_SIMR_STOPIM_EN 0x00000004
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#define I2C_SIMR_STOPIM_DIS 0x00000000
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// Field: [1] STARTIM
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//
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// Start condition interrupt mask
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//
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// 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt
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// controller.
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// 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt
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// controller.
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// ENUMs:
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// EN Enable Interrupt
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// DIS Disable Interrupt
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#define I2C_SIMR_STARTIM 0x00000002
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#define I2C_SIMR_STARTIM_BITN 1
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#define I2C_SIMR_STARTIM_M 0x00000002
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#define I2C_SIMR_STARTIM_S 1
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#define I2C_SIMR_STARTIM_EN 0x00000002
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#define I2C_SIMR_STARTIM_DIS 0x00000000
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// Field: [0] DATAIM
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//
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// Data interrupt mask
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//
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// 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt
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// controller.
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// 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt
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// controller.
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#define I2C_SIMR_DATAIM 0x00000001
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#define I2C_SIMR_DATAIM_BITN 0
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#define I2C_SIMR_DATAIM_M 0x00000001
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#define I2C_SIMR_DATAIM_S 0
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//*****************************************************************************
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//
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// Register: I2C_O_SRIS
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//
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//*****************************************************************************
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// Field: [2] STOPRIS
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//
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// Stop condition raw interrupt status
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//
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// 0: No interrupt
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// 1: A Stop condition interrupt is pending.
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//
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// This bit is cleared by writing a 1 to SICR.STOPIC.
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#define I2C_SRIS_STOPRIS 0x00000004
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#define I2C_SRIS_STOPRIS_BITN 2
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#define I2C_SRIS_STOPRIS_M 0x00000004
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#define I2C_SRIS_STOPRIS_S 2
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// Field: [1] STARTRIS
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//
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// Start condition raw interrupt status
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//
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// 0: No interrupt
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// 1: A Start condition interrupt is pending.
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//
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// This bit is cleared by writing a 1 to SICR.STARTIC.
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#define I2C_SRIS_STARTRIS 0x00000002
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#define I2C_SRIS_STARTRIS_BITN 1
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#define I2C_SRIS_STARTRIS_M 0x00000002
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#define I2C_SRIS_STARTRIS_S 1
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// Field: [0] DATARIS
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//
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// Data raw interrupt status
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//
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// 0: No interrupt
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// 1: A data received or data requested interrupt is pending.
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//
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// This bit is cleared by writing a 1 to the SICR.DATAIC.
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#define I2C_SRIS_DATARIS 0x00000001
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#define I2C_SRIS_DATARIS_BITN 0
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#define I2C_SRIS_DATARIS_M 0x00000001
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#define I2C_SRIS_DATARIS_S 0
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//*****************************************************************************
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//
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// Register: I2C_O_SMIS
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//
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//*****************************************************************************
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// Field: [2] STOPMIS
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//
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// Stop condition masked interrupt status
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//
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// 0: An interrupt has not occurred or is masked/disabled.
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// 1: An unmasked Stop condition interrupt is pending.
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//
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// This bit is cleared by writing a 1 to the SICR.STOPIC.
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#define I2C_SMIS_STOPMIS 0x00000004
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#define I2C_SMIS_STOPMIS_BITN 2
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#define I2C_SMIS_STOPMIS_M 0x00000004
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#define I2C_SMIS_STOPMIS_S 2
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// Field: [1] STARTMIS
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//
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// Start condition masked interrupt status
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//
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// 0: An interrupt has not occurred or is masked/disabled.
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// 1: An unmasked Start condition interrupt is pending.
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//
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// This bit is cleared by writing a 1 to the SICR.STARTIC.
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#define I2C_SMIS_STARTMIS 0x00000002
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#define I2C_SMIS_STARTMIS_BITN 1
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#define I2C_SMIS_STARTMIS_M 0x00000002
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#define I2C_SMIS_STARTMIS_S 1
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// Field: [0] DATAMIS
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//
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// Data masked interrupt status
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//
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// 0: An interrupt has not occurred or is masked/disabled.
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// 1: An unmasked data received or data requested interrupt is pending.
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//
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// This bit is cleared by writing a 1 to the SICR.DATAIC.
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#define I2C_SMIS_DATAMIS 0x00000001
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#define I2C_SMIS_DATAMIS_BITN 0
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#define I2C_SMIS_DATAMIS_M 0x00000001
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#define I2C_SMIS_DATAMIS_S 0
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//*****************************************************************************
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//
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// Register: I2C_O_SICR
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//
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//*****************************************************************************
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// Field: [2] STOPIC
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//
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// Stop condition interrupt clear
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//
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// Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS.
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#define I2C_SICR_STOPIC 0x00000004
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#define I2C_SICR_STOPIC_BITN 2
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#define I2C_SICR_STOPIC_M 0x00000004
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#define I2C_SICR_STOPIC_S 2
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// Field: [1] STARTIC
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//
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// Start condition interrupt clear
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//
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// Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS.
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#define I2C_SICR_STARTIC 0x00000002
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#define I2C_SICR_STARTIC_BITN 1
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#define I2C_SICR_STARTIC_M 0x00000002
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#define I2C_SICR_STARTIC_S 1
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// Field: [0] DATAIC
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//
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// Data interrupt clear
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//
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// Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS.
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#define I2C_SICR_DATAIC 0x00000001
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#define I2C_SICR_DATAIC_BITN 0
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#define I2C_SICR_DATAIC_M 0x00000001
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#define I2C_SICR_DATAIC_S 0
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//*****************************************************************************
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//
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// Register: I2C_O_MSA
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//
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//*****************************************************************************
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// Field: [7:1] SA
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//
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// I2C master slave address
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// Defines which slave is addressed for the transaction in master mode
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#define I2C_MSA_SA_W 7
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#define I2C_MSA_SA_M 0x000000FE
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#define I2C_MSA_SA_S 1
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// Field: [0] RS
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//
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// Receive or Send
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// This bit-field specifies if the next operation is a receive (high) or a
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// transmit/send (low) from the addressed slave SA.
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// ENUMs:
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// RX Receive data from slave
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// TX Transmit/send data to slave
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#define I2C_MSA_RS 0x00000001
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#define I2C_MSA_RS_BITN 0
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#define I2C_MSA_RS_M 0x00000001
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#define I2C_MSA_RS_S 0
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#define I2C_MSA_RS_RX 0x00000001
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#define I2C_MSA_RS_TX 0x00000000
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//*****************************************************************************
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//
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// Register: I2C_O_MSTAT
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//
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//*****************************************************************************
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// Field: [6] BUSBSY
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//
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// Bus busy
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//
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// 0: The I2C bus is idle.
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// 1: The I2C bus is busy.
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//
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// The bit changes based on the MCTRL.START and MCTRL.STOP conditions.
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#define I2C_MSTAT_BUSBSY 0x00000040
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#define I2C_MSTAT_BUSBSY_BITN 6
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#define I2C_MSTAT_BUSBSY_M 0x00000040
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#define I2C_MSTAT_BUSBSY_S 6
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// Field: [5] IDLE
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//
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// I2C idle
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//
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// 0: The I2C controller is not idle.
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// 1: The I2C controller is idle.
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#define I2C_MSTAT_IDLE 0x00000020
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#define I2C_MSTAT_IDLE_BITN 5
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#define I2C_MSTAT_IDLE_M 0x00000020
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#define I2C_MSTAT_IDLE_S 5
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// Field: [4] ARBLST
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//
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// Arbitration lost
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//
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// 0: The I2C controller won arbitration.
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// 1: The I2C controller lost arbitration.
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#define I2C_MSTAT_ARBLST 0x00000010
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#define I2C_MSTAT_ARBLST_BITN 4
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#define I2C_MSTAT_ARBLST_M 0x00000010
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#define I2C_MSTAT_ARBLST_S 4
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// Field: [3] DATACK_N
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//
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// Data Was Not Acknowledge
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//
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// 0: The transmitted data was acknowledged.
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// 1: The transmitted data was not acknowledged.
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#define I2C_MSTAT_DATACK_N 0x00000008
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#define I2C_MSTAT_DATACK_N_BITN 3
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#define I2C_MSTAT_DATACK_N_M 0x00000008
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#define I2C_MSTAT_DATACK_N_S 3
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// Field: [2] ADRACK_N
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//
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// Address Was Not Acknowledge
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//
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// 0: The transmitted address was acknowledged.
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// 1: The transmitted address was not acknowledged.
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#define I2C_MSTAT_ADRACK_N 0x00000004
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#define I2C_MSTAT_ADRACK_N_BITN 2
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#define I2C_MSTAT_ADRACK_N_M 0x00000004
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#define I2C_MSTAT_ADRACK_N_S 2
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// Field: [1] ERR
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//
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// Error
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//
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// 0: No error was detected on the last operation.
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// 1: An error occurred on the last operation.
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#define I2C_MSTAT_ERR 0x00000002
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#define I2C_MSTAT_ERR_BITN 1
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#define I2C_MSTAT_ERR_M 0x00000002
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#define I2C_MSTAT_ERR_S 1
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// Field: [0] BUSY
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//
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// I2C busy
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//
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// 0: The controller is idle.
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// 1: The controller is busy.
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//
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// When this bit-field is set, the other status bits are not valid.
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//
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// Note: The I2C controller requires four SYSBUS clock cycles to assert the
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// BUSY status after I2C master operation has been initiated through MCTRL
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// register.
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// Hence after programming MCTRL register, application is requested to wait for
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// four SYSBUS clock cycles before issuing a controller status inquiry through
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// MSTAT register.
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// Any prior inquiry would result in wrong status being reported.
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#define I2C_MSTAT_BUSY 0x00000001
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#define I2C_MSTAT_BUSY_BITN 0
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#define I2C_MSTAT_BUSY_M 0x00000001
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#define I2C_MSTAT_BUSY_S 0
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//*****************************************************************************
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//
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// Register: I2C_O_MCTRL
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//
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//*****************************************************************************
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// Field: [3] ACK
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//
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// Data acknowledge enable
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//
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// 0: The received data byte is not acknowledged automatically by the master.
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// 1: The received data byte is acknowledged automatically by the master.
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//
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// This bit-field must be cleared when the I2C bus controller requires no
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// further data to be transmitted from the slave transmitter.
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// ENUMs:
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// EN Enable acknowledge
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// DIS Disable acknowledge
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#define I2C_MCTRL_ACK 0x00000008
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#define I2C_MCTRL_ACK_BITN 3
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#define I2C_MCTRL_ACK_M 0x00000008
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#define I2C_MCTRL_ACK_S 3
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#define I2C_MCTRL_ACK_EN 0x00000008
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#define I2C_MCTRL_ACK_DIS 0x00000000
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// Field: [2] STOP
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//
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// This bit-field determines if the cycle stops at the end of the data cycle or
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// continues on to a repeated START condition.
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//
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// 0: The controller does not generate the Stop condition.
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// 1: The controller generates the Stop condition.
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// ENUMs:
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// EN Enable STOP
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// DIS Disable STOP
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#define I2C_MCTRL_STOP 0x00000004
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#define I2C_MCTRL_STOP_BITN 2
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#define I2C_MCTRL_STOP_M 0x00000004
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#define I2C_MCTRL_STOP_S 2
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#define I2C_MCTRL_STOP_EN 0x00000004
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#define I2C_MCTRL_STOP_DIS 0x00000000
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// Field: [1] START
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//
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// This bit-field generates the Start or Repeated Start condition.
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//
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// 0: The controller does not generate the Start condition.
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// 1: The controller generates the Start condition.
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// ENUMs:
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// EN Enable START
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// DIS Disable START
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#define I2C_MCTRL_START 0x00000002
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#define I2C_MCTRL_START_BITN 1
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#define I2C_MCTRL_START_M 0x00000002
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#define I2C_MCTRL_START_S 1
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#define I2C_MCTRL_START_EN 0x00000002
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#define I2C_MCTRL_START_DIS 0x00000000
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// Field: [0] RUN
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//
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// I2C master enable
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//
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// 0: The master is disabled.
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// 1: The master is enabled to transmit or receive data.
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// ENUMs:
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// EN Enable Master
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// DIS Disable Master
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#define I2C_MCTRL_RUN 0x00000001
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#define I2C_MCTRL_RUN_BITN 0
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#define I2C_MCTRL_RUN_M 0x00000001
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#define I2C_MCTRL_RUN_S 0
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#define I2C_MCTRL_RUN_EN 0x00000001
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#define I2C_MCTRL_RUN_DIS 0x00000000
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//*****************************************************************************
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//
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// Register: I2C_O_MDR
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//
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//*****************************************************************************
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// Field: [7:0] DATA
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//
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// When Read: Last RX Data is returned
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// When Written: Data is transferred during TX transaction
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#define I2C_MDR_DATA_W 8
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#define I2C_MDR_DATA_M 0x000000FF
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#define I2C_MDR_DATA_S 0
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//*****************************************************************************
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//
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// Register: I2C_O_MTPR
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//
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//*****************************************************************************
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// Field: [7] TPR_7
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//
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// Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored.
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#define I2C_MTPR_TPR_7 0x00000080
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#define I2C_MTPR_TPR_7_BITN 7
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#define I2C_MTPR_TPR_7_M 0x00000080
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#define I2C_MTPR_TPR_7_S 7
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// Field: [6:0] TPR
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//
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// SCL clock period
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// This field specifies the period of the SCL clock.
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// SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD
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// where:
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// SCL_PRD is the SCL line period (I2C clock).
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// TPR is the timer period register value (range of 1 to 127)
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// SCL_LP is the SCL low period (fixed at 6).
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// SCL_HP is the SCL high period (fixed at 4).
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// CLK_PRD is the system clock period in ns.
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|
#define I2C_MTPR_TPR_W 7
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|
#define I2C_MTPR_TPR_M 0x0000007F
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#define I2C_MTPR_TPR_S 0
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|
|
|
//*****************************************************************************
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|
//
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// Register: I2C_O_MIMR
|
|
//
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|
//*****************************************************************************
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|
// Field: [0] IM
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|
//
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// Interrupt mask
|
|
//
|
|
// 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt
|
|
// controller.
|
|
// 1: The master interrupt is sent to the interrupt controller when the
|
|
// MRIS.RIS is set.
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|
// ENUMs:
|
|
// EN Enable Interrupt
|
|
// DIS Disable Interrupt
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|
#define I2C_MIMR_IM 0x00000001
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|
#define I2C_MIMR_IM_BITN 0
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|
#define I2C_MIMR_IM_M 0x00000001
|
|
#define I2C_MIMR_IM_S 0
|
|
#define I2C_MIMR_IM_EN 0x00000001
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|
#define I2C_MIMR_IM_DIS 0x00000000
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|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: I2C_O_MRIS
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [0] RIS
|
|
//
|
|
// Raw interrupt status
|
|
//
|
|
// 0: No interrupt
|
|
// 1: A master interrupt is pending.
|
|
//
|
|
// This bit is cleared by writing 1 to the MICR.IC bit .
|
|
#define I2C_MRIS_RIS 0x00000001
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|
#define I2C_MRIS_RIS_BITN 0
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|
#define I2C_MRIS_RIS_M 0x00000001
|
|
#define I2C_MRIS_RIS_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: I2C_O_MMIS
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [0] MIS
|
|
//
|
|
// Masked interrupt status
|
|
//
|
|
// 0: An interrupt has not occurred or is masked.
|
|
// 1: A master interrupt is pending.
|
|
//
|
|
// This bit is cleared by writing 1 to the MICR.IC bit .
|
|
#define I2C_MMIS_MIS 0x00000001
|
|
#define I2C_MMIS_MIS_BITN 0
|
|
#define I2C_MMIS_MIS_M 0x00000001
|
|
#define I2C_MMIS_MIS_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: I2C_O_MICR
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [0] IC
|
|
//
|
|
// Interrupt clear
|
|
// Writing 1 to this bit clears MRIS.RIS and MMIS.MIS .
|
|
//
|
|
// Reading this register returns no meaningful data.
|
|
#define I2C_MICR_IC 0x00000001
|
|
#define I2C_MICR_IC_BITN 0
|
|
#define I2C_MICR_IC_M 0x00000001
|
|
#define I2C_MICR_IC_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: I2C_O_MCR
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [5] SFE
|
|
//
|
|
// I2C slave function enable
|
|
// ENUMs:
|
|
// EN Slave mode is enabled.
|
|
// DIS Slave mode is disabled.
|
|
#define I2C_MCR_SFE 0x00000020
|
|
#define I2C_MCR_SFE_BITN 5
|
|
#define I2C_MCR_SFE_M 0x00000020
|
|
#define I2C_MCR_SFE_S 5
|
|
#define I2C_MCR_SFE_EN 0x00000020
|
|
#define I2C_MCR_SFE_DIS 0x00000000
|
|
|
|
// Field: [4] MFE
|
|
//
|
|
// I2C master function enable
|
|
// ENUMs:
|
|
// EN Master mode is enabled.
|
|
// DIS Master mode is disabled.
|
|
#define I2C_MCR_MFE 0x00000010
|
|
#define I2C_MCR_MFE_BITN 4
|
|
#define I2C_MCR_MFE_M 0x00000010
|
|
#define I2C_MCR_MFE_S 4
|
|
#define I2C_MCR_MFE_EN 0x00000010
|
|
#define I2C_MCR_MFE_DIS 0x00000000
|
|
|
|
// Field: [0] LPBK
|
|
//
|
|
// I2C loopback
|
|
//
|
|
// 0: Normal operation
|
|
// 1: Loopback operation (test mode)
|
|
// ENUMs:
|
|
// EN Enable Test Mode
|
|
// DIS Disable Test Mode
|
|
#define I2C_MCR_LPBK 0x00000001
|
|
#define I2C_MCR_LPBK_BITN 0
|
|
#define I2C_MCR_LPBK_M 0x00000001
|
|
#define I2C_MCR_LPBK_S 0
|
|
#define I2C_MCR_LPBK_EN 0x00000001
|
|
#define I2C_MCR_LPBK_DIS 0x00000000
|
|
|
|
|
|
#endif // __I2C__
|