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397 lines
12 KiB
C
397 lines
12 KiB
C
/******************************************************************************
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* Filename: cpu.c
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* Revised: 2018-05-08 10:04:01 +0200 (Tue, 08 May 2018)
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* Revision: 51972
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*
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* Description: Instruction wrappers for special CPU instructions needed by
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* the drivers.
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#include "cc26x0_cpu.h"
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//*****************************************************************************
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//
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// Handle support for DriverLib in ROM:
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// This section will undo prototype renaming made in the header file
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//
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//*****************************************************************************
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#if !defined(DOXYGEN)
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#undef CPUcpsid
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#define CPUcpsid NOROM_CPUcpsid
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#undef CPUprimask
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#define CPUprimask NOROM_CPUprimask
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#undef CPUcpsie
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#define CPUcpsie NOROM_CPUcpsie
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#undef CPUbasepriGet
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#define CPUbasepriGet NOROM_CPUbasepriGet
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#undef CPUdelay
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#define CPUdelay NOROM_CPUdelay
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#endif
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//*****************************************************************************
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//
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// Disable all external interrupts
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//
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//*****************************************************************************
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#if defined(DOXYGEN)
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uint32_t
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CPUcpsid(void)
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{
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// This function is written in assembly. See cpu.c for compiler specific implementation.
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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uint32_t
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CPUcpsid(void)
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{
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// Read PRIMASK and disable interrupts.
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__asm(" mrs r0, PRIMASK\n"
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" cpsid i\n");
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// "Warning[Pe940]: missing return statement at end of non-void function"
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// is suppressed here to avoid putting a "bx lr" in the inline assembly
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// above and a superfluous return statement here.
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#pragma diag_suppress=Pe940
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}
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#pragma diag_default=Pe940
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#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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__asm uint32_t
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CPUcpsid(void)
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{
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// Read PRIMASK and disable interrupts.
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mrs r0, PRIMASK;
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cpsid i;
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bx lr
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}
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#elif defined(__TI_COMPILER_VERSION__)
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uint32_t
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CPUcpsid(void)
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{
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// Read PRIMASK and disable interrupts.
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__asm(" mrs r0, PRIMASK\n"
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" cpsid i\n"
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" bx lr\n");
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// The following keeps the compiler happy, because it wants to see a
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// return value from this function. It will generate code to return
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// a zero. However, the real return is the "bx lr" above, so the
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// return(0) is never executed and the function returns with the value
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// you expect in R0.
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return(0);
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}
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#else
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uint32_t __attribute__((naked))
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CPUcpsid(void)
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{
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uint32_t ui32Ret;
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// Read PRIMASK and disable interrupts
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__asm volatile (" mrs %0, PRIMASK\n"
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" cpsid i\n"
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" bx lr\n"
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: "=r"(ui32Ret)
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);
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// The return is handled in the inline assembly, but the compiler will
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// still complain if there is not an explicit return here (despite the fact
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// that this does not result in any code being produced because of the
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// naked attribute).
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return(ui32Ret);
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}
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#endif
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//*****************************************************************************
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//
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// Get the current interrupt state
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//
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//*****************************************************************************
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#if defined(DOXYGEN)
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uint32_t
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CPUprimask(void)
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{
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// This function is written in assembly. See cpu.c for compiler specific implementation.
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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uint32_t
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CPUprimask(void)
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{
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// Read PRIMASK.
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__asm(" mrs r0, PRIMASK\n");
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// "Warning[Pe940]: missing return statement at end of non-void function"
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// is suppressed here to avoid putting a "bx lr" in the inline assembly
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// above and a superfluous return statement here.
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#pragma diag_suppress=Pe940
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}
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#pragma diag_default=Pe940
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#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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__asm uint32_t
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CPUprimask(void)
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{
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// Read PRIMASK.
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mrs r0, PRIMASK;
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bx lr
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}
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#elif defined(__TI_COMPILER_VERSION__)
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uint32_t
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CPUprimask(void)
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{
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// Read PRIMASK.
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__asm(" mrs r0, PRIMASK\n"
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" bx lr\n");
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// The following keeps the compiler happy, because it wants to see a
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// return value from this function. It will generate code to return
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// a zero. However, the real return is the "bx lr" above, so the
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// return(0) is never executed and the function returns with the value
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// you expect in R0.
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return(0);
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}
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#else
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uint32_t __attribute__((naked))
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CPUprimask(void)
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{
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uint32_t ui32Ret;
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// Read PRIMASK
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__asm volatile (" mrs %0, PRIMASK\n"
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" bx lr\n"
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: "=r"(ui32Ret)
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);
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// The return is handled in the inline assembly, but the compiler will
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// still complain if there is not an explicit return here (despite the fact
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// that this does not result in any code being produced because of the
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// naked attribute).
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return(ui32Ret);
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}
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#endif
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//*****************************************************************************
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//
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// Enable all external interrupts
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//
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//*****************************************************************************
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#if defined(DOXYGEN)
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uint32_t
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CPUcpsie(void)
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{
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// This function is written in assembly. See cpu.c for compiler specific implementation.
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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uint32_t
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CPUcpsie(void)
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{
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// Read PRIMASK and enable interrupts.
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__asm(" mrs r0, PRIMASK\n"
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" cpsie i\n");
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// "Warning[Pe940]: missing return statement at end of non-void function"
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// is suppressed here to avoid putting a "bx lr" in the inline assembly
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// above and a superfluous return statement here.
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#pragma diag_suppress=Pe940
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}
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#pragma diag_default=Pe940
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#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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__asm uint32_t
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CPUcpsie(void)
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{
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// Read PRIMASK and enable interrupts.
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mrs r0, PRIMASK;
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cpsie i;
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bx lr
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}
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#elif defined(__TI_COMPILER_VERSION__)
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uint32_t
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CPUcpsie(void)
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{
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// Read PRIMASK and enable interrupts.
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__asm(" mrs r0, PRIMASK\n"
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" cpsie i\n"
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" bx lr\n");
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// The following keeps the compiler happy, because it wants to see a
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// return value from this function. It will generate code to return
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// a zero. However, the real return is the "bx lr" above, so the
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// return(0) is never executed and the function returns with the value
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// you expect in R0.
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return(0);
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}
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#else
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uint32_t __attribute__((naked))
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CPUcpsie(void)
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{
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uint32_t ui32Ret;
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// Read PRIMASK and enable interrupts.
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__asm volatile (" mrs %0, PRIMASK\n"
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" cpsie i\n"
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" bx lr\n"
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: "=r"(ui32Ret)
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);
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// The return is handled in the inline assembly, but the compiler will
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// still complain if there is not an explicit return here (despite the fact
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// that this does not result in any code being produced because of the
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// naked attribute).
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return(ui32Ret);
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}
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#endif
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//*****************************************************************************
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//
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// Get the interrupt priority disable level
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//
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//*****************************************************************************
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#if defined(DOXYGEN)
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uint32_t
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CPUbasepriGet(void)
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{
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// This function is written in assembly. See cpu.c for compiler specific implementation.
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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uint32_t
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CPUbasepriGet(void)
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{
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// Read BASEPRI.
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__asm(" mrs r0, BASEPRI\n");
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// "Warning[Pe940]: missing return statement at end of non-void function"
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// is suppressed here to avoid putting a "bx lr" in the inline assembly
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// above and a superfluous return statement here.
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#pragma diag_suppress=Pe940
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}
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#pragma diag_default=Pe940
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#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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__asm uint32_t
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CPUbasepriGet(void)
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{
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// Read BASEPRI.
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mrs r0, BASEPRI;
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bx lr
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}
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#elif defined(__TI_COMPILER_VERSION__)
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uint32_t
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CPUbasepriGet(void)
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{
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// Read BASEPRI.
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__asm(" mrs r0, BASEPRI\n"
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" bx lr\n");
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// The following keeps the compiler happy, because it wants to see a
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// return value from this function. It will generate code to return
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// a zero. However, the real return is the "bx lr" above, so the
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// return(0) is never executed and the function returns with the value
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// you expect in R0.
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return(0);
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}
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#else
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uint32_t __attribute__((naked))
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CPUbasepriGet(void)
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{
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uint32_t ui32Ret;
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// Read BASEPRI.
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__asm volatile (" mrs %0, BASEPRI\n"
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" bx lr\n"
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: "=r"(ui32Ret)
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);
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// The return is handled in the inline assembly, but the compiler will
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// still complain if there is not an explicit return here (despite the fact
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// that this does not result in any code being produced because of the
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// naked attribute).
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return(ui32Ret);
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}
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#endif
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//*****************************************************************************
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//
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// Provide a small delay
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//
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//*****************************************************************************
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#if defined(DOXYGEN)
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void
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CPUdelay(uint32_t ui32Count)
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{
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// This function is written in assembly. See cpu.c for compiler specific implementation.
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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void
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CPUdelay(uint32_t ui32Count)
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{
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// Loop the specified number of times
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__asm("CPUdelay:\n"
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" subs r0, #1\n"
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" bne.n CPUdelay\n"
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" bx lr");
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#pragma diag_suppress=Pe940
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}
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#pragma diag_default=Pe940
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#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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__asm void
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CPUdelay(uint32_t ui32Count)
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{
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// Delay the specified number of times (3 cycles pr. loop)
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CPUdel
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subs r0, #1;
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bne CPUdel;
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bx lr;
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}
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#elif defined(__TI_COMPILER_VERSION__)
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// For CCS implement this function in pure assembly. This prevents the TI
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// compiler from doing funny things with the optimizer.
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// Loop the specified number of times
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__asm(" .sect \".text:NOROM_CPUdelay\"\n"
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" .clink\n"
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" .thumbfunc NOROM_CPUdelay\n"
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" .thumb\n"
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" .global NOROM_CPUdelay\n"
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"NOROM_CPUdelay:\n"
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" subs r0, #1\n"
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" bne.n NOROM_CPUdelay\n"
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" bx lr\n");
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#else
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// GCC
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void __attribute__((naked))
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CPUdelay(uint32_t ui32Count)
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{
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// Loop the specified number of times
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__asm volatile ("%=: subs %0, #1\n"
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" bne %=b\n"
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" bx lr\n"
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: /* No output */
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: "r" (ui32Count)
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);
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}
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#endif
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